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AD9834BRUZ

Analog Devices · Direct Digital Synthesis (DDS) · TSSOP-20

AD9834BRUZ from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FS ADJUST passive Full-scale adjust control. An external resistor R_SET (typ 6.8 kΩ) is connected from this pin to AGND to set the DAC full-scale output current: IOUT_FS = 18 x FSADJUST/R_SET, with FSADJUST = 1.15 V nominal.
2 REFOUT output Voltage reference output. The AD9834 provides an internal 1.20 V reference on this pin. REFOUT output impedance is typically 1 kΩ (as source). Higher impedance when sinking.
3 COMP passive DAC bias pin. Used for decoupling the DAC bias voltage.
4 AVDD power_in Positive analog supply, 2.3 V to 5.5 V. Decouple with a 0.1 µF capacitor to AGND.
5 DVDD power_in Positive digital supply, 2.3 V to 5.5 V. Decouple with a 0.1 µF capacitor to DGND.
6 CAP/2.5V passive Internal digital core 2.5 V regulator node. When DVDD > 2.7 V, an on-chip regulator generates 2.5 V for digital logic from DVDD; decouple with a typical 100 nF capacitor from CAP/2.5V to DGND. If DVDD ≤ 2.7 V, tie CAP/2.5V directly to DVDD.
7 DGND power_in Digital ground return.
8 MCLK input Digital master clock input. The DDS output frequency is a binary fraction of MCLK; both output frequency accuracy and phase noise are determined by this clock. Max 75 MHz.
9 FSELECT input Frequency select input. Controls which frequency register (FREQ0 or FREQ1) is used in the phase accumulator. Can be overridden by control bit FSEL. If FSEL is used, FSELECT should be tied to CMOS high or low.
10 PSELECT input Phase select input. Controls which phase register (PHASE0 or PHASE1) is added to the phase accumulator output. Can be overridden by control bit PSEL. If PSEL is used, PSELECT should be tied to CMOS high or low.
11 RESET input Active-high digital reset input. Resets appropriate internal registers to 0, providing an analog output of midscale. RESET does not affect any of the addressable registers.
12 SLEEP input Active-high digital input. When high, the DAC is powered down. Functionally identical to control-register bit SLEEP12.
13 SDATA input Serial data input. 16-bit serial data words are applied to this input.
14 SCLK input Serial clock input. Data is clocked into the AD9834 on each SCLK falling edge. Max 40 MHz.
15 FSYNC input Active-low control (frame sync) input. Frames a serial data word transfer; when FSYNC goes low, the device is alerted that a new data word is being loaded.
16 SIGN BIT OUT output Logic output. The comparator output is available on this pin, or the MSB of the NCO can be output. Enabled by setting control-bit OPBITEN = 1. Bit SIGN/PIB selects whether the comparator output or the NCO MSB is driven out.
17 VIN input Comparator input. The filtered sinusoidal DAC output can be applied to VIN to produce a square wave. When control bits OPBITEN=1 and SIGN/PIB=1, the comparator input is connected to VIN.
18 AGND power_in Analog ground return.
19 IOUT output Current output of the 10-bit DAC. A nominal 200 Ω external load resistor should be connected between IOUT and AGND. A 20 pF capacitor to AGND is also recommended to help suppress clock feedthrough. Full-scale current typically 3 mA.
20 IOUTB output Complementary current output. Can be connected to AGND via a nominal 200 Ω load resistor, or tied directly to AGND.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-20
Category Data Acquisition
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • AD9834BRUZ
  • AD9834BRUZCRUZ
  • AD9834BRUZCRU

CAD (KiCad official)

  • Symbol: AD9834BRUZ
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (36 pp, sha256 8fdc5082ce1704cb, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF