AD7811YRUZ-REEL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VREF	input	External reference input. When using an external precision reference or tying VREF to VDD, the EXTREF bit in the control register must be set to logic 1. External reference input range is 1.2 V to VDD.
2	CREF	passive	Reference decoupling capacitor pin. A 10 nF capacitor is connected here to improve the noise performance of the on-chip 2.5 V reference.
3	VIN1	input	Analog Input Channel 1. Input range is 0 V to VREF. Can be used as single-ended, pseudo-differential with respect to VIN4 (common), or as the (+) input of the VIN1/VIN2 pseudo-differential pair.
4	AGND	power_in	Analog Ground. Ground reference for the track/hold, comparator, on-chip reference, and charge-redistribution DAC.
5	VIN2	input	Analog Input Channel 2. Input range is 0 V to VREF. Can be used as single-ended, pseudo-differential to VIN4, or as the (-) input of the VIN1/VIN2 pseudo-differential pair.
6	VIN3	input	Analog Input Channel 3. Input range is 0 V to VREF. Can be used as single-ended, pseudo-differential to VIN4, or as the (+) input of the VIN3/VIN4 pseudo-differential pair.
7	VIN4	input	Analog Input Channel 4. Input range is 0 V to VREF. Also serves as the common reference for pseudo-differential mode (with VIN4/AGND control bit = 1) or as the (-) input of the VIN3/VIN4 pseudo-differential pair.
8	A0	input	Package Address Pin. Logic input hardwired high or low; used with the package-address bit in the control register to let two devices share the same serial bus in a multipackage application (e.g., an AD7811 and an AD7812 for a 12-channel system).
9	DGND	power_in	Digital Ground. Ground reference for all digital circuitry. AGND and DGND should be connected together at the device for good noise suppression.
10	TFS	input	Transmit Frame Sync (active low). The falling edge tells the part that a new 10-bit control word will be shifted in on the next 10 falling edges of SCLK.
11	RFS	input	Receive Frame Sync. Rising edge enables the internal serial-interface counter for compatibility with DSPs that use a continuous SCLK and framing signal; also acts as a serial bus-select in multipackage applications. The counter resets at the end of a serial read.
12	DOUT	tri_state	Serial Data Output. Conversion data is shifted out on the rising edge of SCLK. Output enters high impedance on the rising edge of the 11th SCLK pulse.
13	DIN	input	Serial Data Input. The 10-bit control word is shifted in on this pin; 13 SCLK pulses are needed to complete a serial write (only the first 10 bits are latched).
14	SCLK	input	Serial Clock Input. External serial clock used to shift data in and out of the device. DOUT data is clocked out on the rising edge; DIN data is latched on the falling edge.
15	CONVST	input	Convert Start (edge-triggered). The track/hold enters hold mode on the falling edge and a conversion is initiated. The state of this pin at the end of conversion also determines whether the part enters power-down.
16	VDD	power_in	Positive Supply Voltage, 2.7 V to 5.5 V. Typical current consumption is 3.5 mA (max) in normal operation; 1 µA (max) in full power-down. Decouple to AGND close to the pin.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16
Category	Data Acquisition
Pins	16

Ordering variants

Same part, different packaging or reel option.

AD7811YRUZ-REEL7
AD7811YRUZ-REEL7YRZ
AD7811YRUZ-REEL7YN
AD7811YRUZ-REEL7YNZ

CAD (KiCad official)

Symbol: AD7811YRUZ-REEL7
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 4f6999952afd9e01, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF