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74VHC595PW118

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by Ray

Nexperia Shift Registers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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74VHC595PW118

Nexperia · Shift Registers · TSSOP-16

74VHC595PW118 from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output bit 1 from the 8-bit storage register. 3-state bus driver output; enabled when OE is LOW, high-impedance when OE is HIGH.
2 Q2 tri_state Parallel data output bit 2 from the 8-bit storage register. 3-state bus driver output; enabled when OE is LOW, high-impedance when OE is HIGH.
3 Q3 tri_state Parallel data output bit 3 from the 8-bit storage register. 3-state bus driver output; enabled when OE is LOW, high-impedance when OE is HIGH.
4 Q4 tri_state Parallel data output bit 4 from the 8-bit storage register. 3-state bus driver output; enabled when OE is LOW, high-impedance when OE is HIGH.
5 Q5 tri_state Parallel data output bit 5 from the 8-bit storage register. 3-state bus driver output; enabled when OE is LOW, high-impedance when OE is HIGH.
6 Q6 tri_state Parallel data output bit 6 from the 8-bit storage register. 3-state bus driver output; enabled when OE is LOW, high-impedance when OE is HIGH.
7 Q7 tri_state Parallel data output bit 7 (MSB) from the 8-bit storage register. 3-state bus driver output; enabled when OE is LOW, high-impedance when OE is HIGH.
8 GND power_in Ground reference (0 V). Connect to system ground.
9 Q7S output Serial data output for cascading. Outputs the previous state of internal shift register stage 6 (Q6S), allowing cascade connection to the DS input of the next 74VHC595 to build wider shift registers.
10 MR input Master reset input (active LOW). When LOW, asynchronously clears all 8 shift register stages; does not affect the storage register directly.
11 SHCP input Shift register clock input. Data on DS is shifted into the shift register on the positive-going (rising) edge of SHCP. Schmitt-trigger input.
12 STCP input Storage register clock input (latch clock). On a positive-going edge, the contents of the shift register are transferred to the 8-bit storage register/parallel outputs. Schmitt-trigger input.
13 OE input Output enable input (active LOW). When LOW, the storage register contents drive Q0..Q7; when HIGH, Q0..Q7 are placed in the high-impedance (3-state) OFF-state.
14 DS input Serial data input to the shift register. Sampled on the rising edge of SHCP into stage 0 of the 8-stage shift register. Schmitt-trigger input.
15 Q0 tri_state Parallel data output bit 0 (LSB) from the 8-bit storage register. 3-state bus driver output; enabled when OE is LOW, high-impedance when OE is HIGH.
16 VCC power_in Supply voltage. 2.0 V to 5.5 V for 74VHC595; 4.5 V to 5.5 V for 74VHCT595. Decouple locally with a 0.1 uF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74VHC595PW118
  • 74VHC595PW118D
  • 74VHC595PW118BQ

CAD (KiCad official)

  • Symbol: 74VHC595PW118
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (None pp, sha256 41d819c450dfa203, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF