74LVC541APW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE1	input	Output enable input 1 (active LOW). When OE1 is LOW and OE2 is LOW, the Yn outputs follow the An inputs; a HIGH on OE1 forces all Yn outputs to high-impedance 3-state.
2	A0	input	Data input bit 0 to buffer channel 0. 5 V tolerant Schmitt-trigger CMOS input; drives output Y0 when the device is enabled.
3	A1	input	Data input bit 1 to buffer channel 1. 5 V tolerant Schmitt-trigger CMOS input; drives output Y1 when the device is enabled.
4	A2	input	Data input bit 2 to buffer channel 2. 5 V tolerant Schmitt-trigger CMOS input; drives output Y2 when the device is enabled.
5	A3	input	Data input bit 3 to buffer channel 3. 5 V tolerant Schmitt-trigger CMOS input; drives output Y3 when the device is enabled.
6	A4	input	Data input bit 4 to buffer channel 4. 5 V tolerant Schmitt-trigger CMOS input; drives output Y4 when the device is enabled.
7	A5	input	Data input bit 5 to buffer channel 5. 5 V tolerant Schmitt-trigger CMOS input; drives output Y5 when the device is enabled.
8	A6	input	Data input bit 6 to buffer channel 6. 5 V tolerant Schmitt-trigger CMOS input; drives output Y6 when the device is enabled.
9	A7	input	Data input bit 7 to buffer channel 7. 5 V tolerant Schmitt-trigger CMOS input; drives output Y7 when the device is enabled.
10	GND	power_in	Ground reference (0 V). Common return for supply and logic signals.
11	Y7	tri_state	Bus output bit 7 from buffer channel 7. 3-state CMOS output; drives up to ±24 mA at VCC = 3.0 V, high-impedance when OE1 or OE2 is HIGH.
12	Y6	tri_state	Bus output bit 6 from buffer channel 6. 3-state CMOS output; drives up to ±24 mA at VCC = 3.0 V, high-impedance when OE1 or OE2 is HIGH.
13	Y5	tri_state	Bus output bit 5 from buffer channel 5. 3-state CMOS output; drives up to ±24 mA at VCC = 3.0 V, high-impedance when OE1 or OE2 is HIGH.
14	Y4	tri_state	Bus output bit 4 from buffer channel 4. 3-state CMOS output; drives up to ±24 mA at VCC = 3.0 V, high-impedance when OE1 or OE2 is HIGH.
15	Y3	tri_state	Bus output bit 3 from buffer channel 3. 3-state CMOS output; drives up to ±24 mA at VCC = 3.0 V, high-impedance when OE1 or OE2 is HIGH.
16	Y2	tri_state	Bus output bit 2 from buffer channel 2. 3-state CMOS output; drives up to ±24 mA at VCC = 3.0 V, high-impedance when OE1 or OE2 is HIGH.
17	Y1	tri_state	Bus output bit 1 from buffer channel 1. 3-state CMOS output; drives up to ±24 mA at VCC = 3.0 V, high-impedance when OE1 or OE2 is HIGH.
18	Y0	tri_state	Bus output bit 0 from buffer channel 0. 3-state CMOS output; drives up to ±24 mA at VCC = 3.0 V, high-impedance when OE1 or OE2 is HIGH.
19	OE2	input	Output enable input 2 (active LOW). When OE2 is LOW and OE1 is LOW, the Yn outputs follow the An inputs; a HIGH on OE2 forces all Yn outputs to high-impedance 3-state.
20	VCC	power_in	Positive supply voltage. Recommended range 1.65 V to 3.6 V (functional down to 1.2 V); absolute maximum 6.5 V. Decouple to GND close to the pin.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	TSSOP-20
Category	Logic
Pins	20

Ordering variants

Same part, different packaging or reel option.

74LVC541APW
74LVC541APWD
74LVC541APWBQ

CAD (KiCad official)

Symbol: 74LVC541APW
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (14 pp, sha256 33cdbbe38f7bdda9, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF