74LVC1G74DC from Nexperia, in a VSSOP-8-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CP	input	Clock input. Positive edge-triggered (LOW-to-HIGH transition) with Schmitt-trigger action; data on D is captured to Q on the rising edge.
2	D	input	Data input. Sampled by the flip-flop on the LOW-to-HIGH edge of CP and driven to the Q output when setup/hold requirements are met.
3	~Q	output	Complementary (inverted) output. Drives ±24 mA at VCC = 3.0 V; complement of Q.
4	GND	power_in	Ground reference (0 V).
5	Q	output	True output. Drives ±24 mA at VCC = 3.0 V; reflects the captured D value after each CP rising edge (subject to SD/RD overrides).
6	~RD	input	Asynchronous reset-direct input, active LOW. Forces Q LOW and ~Q HIGH regardless of CP and D.
7	~SD	input	Asynchronous set-direct input, active LOW. Forces Q HIGH and ~Q LOW regardless of CP and D. When both ~SD and ~RD are LOW, both outputs go HIGH.
8	VCC	power_in	Supply voltage. Recommended operating range 1.65 V to 5.5 V (absolute maximum 6.5 V). Bypass with a local decoupling capacitor.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	VSSOP-8-0.5mm
Category	Logic
Pins	8

Ordering variants

74LVC1G74DC
74LVC1G74DCDP
74LVC1G74DCGT
74LVC1G74DCGF
74LVC1G74DCGN
74LVC1G74DCGS

CAD (KiCad official)

Symbol: 74LVC1G74DC
Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
3D model: VSSOP-8-0.5mm (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (19 pp, sha256 a601aca999c05cc2, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF