74LVC1G00M7 from HGSEMI, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A	input	Logic input A of the 2-input NAND gate. CMOS input; VIH ≥ 0.7VCC and VIL ≤ 0.3VCC at VCC = 3-5.5 V. Input leakage current ~0.01 uA typ (±5 uA max).
2	B	input	Logic input B of the 2-input NAND gate. CMOS input; VIH ≥ 0.7VCC and VIL ≤ 0.3VCC at VCC = 3-5.5 V. Input leakage current ~0.01 uA typ (±5 uA max).
3	GND	power_in	Ground reference (0 V) for the device.
4	Y	output	NAND gate output: Y = NOT(A AND B). Push-pull CMOS output; sources up to 32 mA and sinks up to 32 mA at VCC = 4.5 V. Absolute max per-pin output current 25 mA (recommended).
5	VCC	power_in	Positive supply input. Operating range 1.65 V to 5.5 V; absolute maximum 6.5 V. Bypass with a ceramic capacitor placed close to the pin.

Key specifications

Parameter	Value
Manufacturer	HGSEMI
Package	SC-70-5
Category	Logic
Pins	5

Ordering variants

Same part, different packaging or reel option.

74LVC1G00M7
74LVC1G00M7/TR
74LVC1G00M7M5
74LVC1G00M7M5/TR

CAD (KiCad official)

Symbol: 74LVC1G00M7
Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
3D model: SC-70-5 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HGSEMI datasheet (8 pp, sha256 c6654ee8f8b8fc1b, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF