component

74LVC161PW

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by Ray

Nexperia Counters, Dividers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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74LVC161PW

Nexperia · Counters, Dividers · TSSOP-16

74LVC161PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Synchronous master reset (active LOW). A LOW level asynchronously forces all flip-flop outputs Q0-Q3 LOW regardless of the levels at CP, PE, CET, and CEP.
2 CP input Clock input, LOW-to-HIGH edge-triggered. All flip-flops are clocked simultaneously on the positive-going edge of CP.
3 D0 input Parallel data input bit 0. Loaded into the counter on the positive-going edge of CP when PE is LOW.
4 D1 input Parallel data input bit 1. Loaded into the counter on the positive-going edge of CP when PE is LOW.
5 D2 input Parallel data input bit 2. Loaded into the counter on the positive-going edge of CP when PE is LOW.
6 D3 input Parallel data input bit 3. Loaded into the counter on the positive-going edge of CP when PE is LOW.
7 CEP input Count enable input. Must be HIGH together with CET to allow the counter to advance on the next CP edge.
8 GND power_in Ground reference (0 V).
9 PE input Parallel enable input (active LOW). A LOW level disables counting and causes the data at D0-D3 to be loaded into the counter on the next positive-going CP edge (subject to setup/hold requirements).
10 CET input Count enable carry input. Must be HIGH together with CEP to allow counting; CET is also fed forward to enable the terminal count (TC) output.
11 Q3 output Flip-flop output bit 3 (MSB). Preset to the level at D3 during a parallel load and cleared LOW by MR.
12 Q2 output Flip-flop output bit 2. Preset to the level at D2 during a parallel load and cleared LOW by MR.
13 Q1 output Flip-flop output bit 1. Preset to the level at D1 during a parallel load and cleared LOW by MR.
14 Q0 output Flip-flop output bit 0 (LSB). Preset to the level at D0 during a parallel load and cleared LOW by MR.
15 TC output Terminal count output. Produces a HIGH pulse of duration approximately equal to a HIGH-level output of Q0 when the counter reaches its terminal count with CET HIGH; used to enable the next cascaded stage.
16 VCC power_in Supply voltage. Wide operating range from 1.2 V to 3.6 V; inputs are 5 V tolerant.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74LVC161PW
  • 74LVC161PWD
  • 74LVC161PWDB
  • 74LVC161PWBQ

CAD (KiCad official)

  • Symbol: 74LVC161PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (22 pp, sha256 0f33287ae3d8c662, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF