74LCX00FT from TOSHIBA, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Gate 1, input A. CMOS input with 5-V tolerance (VIN 0 to 5.5 V). High-level input voltage VIH = VCC x 0.9 min (1.65-2.3 V range).
2	1B	input	Gate 1, input B. CMOS input with 5-V tolerance. Pairs with 1A into the first NAND gate.
3	1Y	output	Gate 1 NAND output. Y = NAND(1A, 1B). Drives
4	2A	input	Gate 2, input A. CMOS input with 5-V tolerance.
5	2B	input	Gate 2, input B. CMOS input with 5-V tolerance.
6	2Y	output	Gate 2 NAND output. Y = NAND(2A, 2B). Drives 24 mA min at VCC = 3.0 V.
7	GND	power_in	Ground reference (0 V) for the device.
8	3Y	output	Gate 3 NAND output. Y = NAND(3A, 3B). Drives 24 mA min at VCC = 3.0 V.
9	3A	input	Gate 3, input A. CMOS input with 5-V tolerance.
10	3B	input	Gate 3, input B. CMOS input with 5-V tolerance.
11	4Y	output	Gate 4 NAND output. Y = NAND(4A, 4B). Drives 24 mA min at VCC = 3.0 V.
12	4A	input	Gate 4, input A. CMOS input with 5-V tolerance.
13	4B	input	Gate 4, input B. CMOS input with 5-V tolerance.
14	VCC	power_in	Positive supply voltage. Operating range VCC = 1.65 to 3.6 V (absolute max 6.5 V). Bypass with a 0.1 uF ceramic close to the pin.

Key specifications

Parameter	Value
Manufacturer	TOSHIBA
Package	TSSOP-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

74LCX00FT

CAD (KiCad official)

Symbol: 74LCX00FT
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: TOSHIBA datasheet (8 pp, sha256 0449fc2857d4ecdd, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF