component
74hct30pw
Public Unreviewedby Ray
Nexperia Gates, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdown74HCT30PW
Nexperia · Gates · TSSOP-14
74HCT30PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Data input A of the 8-input NAND gate. TTL-level input (VIH min 2.0 V, VIL max 0.8 V at VCC = 4.5 V to 5.5 V). Includes input clamp diode. |
| 2 | B | input | Data input B of the 8-input NAND gate. TTL-level input (VIH min 2.0 V, VIL max 0.8 V at VCC = 4.5 V to 5.5 V). Includes input clamp diode. |
| 3 | C | input | Data input C of the 8-input NAND gate. TTL-level input (VIH min 2.0 V, VIL max 0.8 V at VCC = 4.5 V to 5.5 V). Includes input clamp diode. |
| 4 | D | input | Data input D of the 8-input NAND gate. TTL-level input (VIH min 2.0 V, VIL max 0.8 V at VCC = 4.5 V to 5.5 V). Includes input clamp diode. |
| 5 | E | input | Data input E of the 8-input NAND gate. TTL-level input (VIH min 2.0 V, VIL max 0.8 V at VCC = 4.5 V to 5.5 V). Includes input clamp diode. |
| 6 | F | input | Data input F of the 8-input NAND gate. TTL-level input (VIH min 2.0 V, VIL max 0.8 V at VCC = 4.5 V to 5.5 V). Includes input clamp diode. |
| 7 | GND | power_in | Ground (0 V) reference for the device. All voltages are referenced to this pin. |
| 8 | Y | output | Data output. Y is LOW only when all eight inputs A-H are HIGH; otherwise Y is HIGH. Typical drive: IO up to ±4.0 mA at VCC = 4.5 V with VOH ≥ 3.98 V / VOL ≤ 0.26 V. |
| 9 | n.c. | unconnected | Not connected. Pin has no internal bond; may be left floating or tied for board layout convenience. |
| 10 | n.c. | unconnected | Not connected. Pin has no internal bond; may be left floating or tied for board layout convenience. |
| 11 | G | input | Data input G of the 8-input NAND gate. TTL-level input (VIH min 2.0 V, VIL max 0.8 V at VCC = 4.5 V to 5.5 V). Includes input clamp diode. |
| 12 | H | input | Data input H of the 8-input NAND gate. TTL-level input (VIH min 2.0 V, VIL max 0.8 V at VCC = 4.5 V to 5.5 V). Includes input clamp diode. |
| 13 | n.c. | unconnected | Not connected. Pin has no internal bond; may be left floating or tied for board layout convenience. |
| 14 | VCC | power_in | Positive supply voltage. Recommended operating range 4.5 V to 5.5 V (74HCT30); absolute maximum -0.5 V to +7 V. Bypass to GND with a 100 nF ceramic capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
74HCT30PW74HCT30PWD
CAD (KiCad official)
- Symbol:
74HCT30PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (None pp, sha256
461f481b50017bf4, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).