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74HCT273PW-Q100J

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by Ray

Nexperia Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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74HCT273PW-Q100J

Nexperia · Flip Flops · TSSOP-20

74HCT273PW-Q100J from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Active-LOW master reset. A LOW forces all Qn outputs LOW asynchronously and independently of CP and Dn. TTL-level input (VIH >= 2.0 V, VIL <= 0.8 V at VCC = 4.5-5.5 V).
2 Q0 output Flip-flop 0 output; assumes the state of D0 sampled one set-up time before the LOW-to-HIGH CP edge. IOH/IOL rated to +/-5.2 mA (VCC = 5.5 V). Forced LOW when MR = LOW.
3 D0 input Data input to flip-flop 0. Sampled at the LOW-to-HIGH CP edge; must meet tsu (12 ns typ, VCC = 4.5 V) and th (3 ns) requirements. TTL-compatible input.
4 D1 input Data input to flip-flop 1. Sampled at the LOW-to-HIGH CP edge; must meet tsu/th timing. TTL-compatible input.
5 Q1 output Flip-flop 1 output; assumes the state of D1 at the LOW-to-HIGH CP edge. IOH/IOL rated to +/-5.2 mA. Forced LOW when MR = LOW.
6 Q2 output Flip-flop 2 output; assumes the state of D2 at the LOW-to-HIGH CP edge. IOH/IOL rated to +/-5.2 mA. Forced LOW when MR = LOW.
7 D2 input Data input to flip-flop 2. Sampled at the LOW-to-HIGH CP edge; must meet tsu/th timing. TTL-compatible input.
8 D3 input Data input to flip-flop 3. Sampled at the LOW-to-HIGH CP edge; must meet tsu/th timing. TTL-compatible input.
9 Q3 output Flip-flop 3 output; assumes the state of D3 at the LOW-to-HIGH CP edge. IOH/IOL rated to +/-5.2 mA. Forced LOW when MR = LOW.
10 GND power_in Ground reference (0 V). All voltages are referenced to this pin.
11 CP input Common clock input for all eight flip-flops. Positive-edge triggered (LOW-to-HIGH). fmax = 30 MHz min (24 MHz over full auto temp range) at VCC = 4.5 V; TTL-compatible input.
12 Q4 output Flip-flop 4 output; assumes the state of D4 at the LOW-to-HIGH CP edge. IOH/IOL rated to +/-5.2 mA. Forced LOW when MR = LOW.
13 D4 input Data input to flip-flop 4. Sampled at the LOW-to-HIGH CP edge; must meet tsu/th timing. TTL-compatible input.
14 D5 input Data input to flip-flop 5. Sampled at the LOW-to-HIGH CP edge; must meet tsu/th timing. TTL-compatible input.
15 Q5 output Flip-flop 5 output; assumes the state of D5 at the LOW-to-HIGH CP edge. IOH/IOL rated to +/-5.2 mA. Forced LOW when MR = LOW.
16 Q6 output Flip-flop 6 output; assumes the state of D6 at the LOW-to-HIGH CP edge. IOH/IOL rated to +/-5.2 mA. Forced LOW when MR = LOW.
17 D6 input Data input to flip-flop 6. Sampled at the LOW-to-HIGH CP edge; must meet tsu/th timing. TTL-compatible input.
18 D7 input Data input to flip-flop 7. Sampled at the LOW-to-HIGH CP edge; must meet tsu/th timing. TTL-compatible input.
19 Q7 output Flip-flop 7 output; assumes the state of D7 at the LOW-to-HIGH CP edge. IOH/IOL rated to +/-5.2 mA. Forced LOW when MR = LOW.
20 VCC power_in Positive supply voltage. Recommended range 4.5 V to 5.5 V for the HCT variant (absolute max 7 V). Bypass with a 100 nF ceramic close to the pin.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • 74HCT273PW-Q100J
  • 74HC273PW-Q100
  • 74HCT273D-Q100
  • 74HC273D-Q100
  • 74HCT273BQ-Q100
  • 74HC273BQ-Q100

CAD (KiCad official)

  • Symbol: 74HCT273PW-Q100J
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 194a6eee5134476b, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF