component

74HCT123D

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by Ray

Nexperia Monostable Multivibrators, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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74HCT123D

Nexperia · Monostable Multivibrators · SOIC-16

74HCT123D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Negative-edge triggered input 1 (Schmitt-trigger). Falling edge on this pin triggers monostable 1 when 1B is HIGH and 1RD is HIGH.
2 1B input Positive-edge triggered input 1 (Schmitt-trigger). Rising edge on this pin triggers monostable 1 when 1A is LOW and 1RD is HIGH.
3 1RD input Direct reset input 1 (active LOW) and positive-edge triggered input 1. LOW forces output 1Q LOW; a LOW-to-HIGH transition with 1A LOW and 1B HIGH triggers the monostable.
4 1Q output Active-LOW output 1 (complementary output of monostable 1). Sits HIGH in the untriggered state and pulses LOW during the timed output pulse.
5 2Q output Active-HIGH output 2 of monostable 2. Sits LOW in the untriggered state and pulses HIGH for the programmed pulse width when triggered.
6 2CEXT passive External timing capacitor connection for monostable 2. Connect CEXT between this pin and 2REXT/CEXT (pin 7) to set the output pulse width together with REXT.
7 2REXT/CEXT passive External resistor and capacitor common node for monostable 2. Connect REXT from this pin to VCC and CEXT from this pin to 2CEXT (pin 6) to program pulse width tW ≈ 0.45 × REXT × CEXT (HC family).
8 GND power_in Ground reference (0 V). Common return for all internal circuitry.
9 2A input Negative-edge triggered input 2 (Schmitt-trigger). Falling edge on this pin triggers monostable 2 when 2B is HIGH and 2RD is HIGH.
10 2B input Positive-edge triggered input 2 (Schmitt-trigger). Rising edge on this pin triggers monostable 2 when 2A is LOW and 2RD is HIGH.
11 2RD input Direct reset input 2 (active LOW) and positive-edge triggered input 2. LOW forces output 2Q LOW; a LOW-to-HIGH transition with 2A LOW and 2B HIGH triggers the monostable.
12 2Q output Active-LOW output 2 (complementary output of monostable 2). Sits HIGH in the untriggered state and pulses LOW during the timed output pulse.
13 1Q output Active-HIGH output 1 of monostable 1. Sits LOW in the untriggered state and pulses HIGH for the programmed pulse width when triggered.
14 1CEXT passive External timing capacitor connection for monostable 1. Connect CEXT between this pin and 1REXT/CEXT (pin 15) to set the output pulse width together with REXT.
15 1REXT/CEXT passive External resistor and capacitor common node for monostable 1. Connect REXT from this pin to VCC and CEXT from this pin to 1CEXT (pin 14) to program pulse width tW ≈ 0.45 × REXT × CEXT (HC family).
16 VCC power_in Supply voltage. Operating range 2.0 V to 6.0 V for 74HC123; 4.5 V to 5.5 V (JESD8C: 2.7 V to 3.6 V also supported) for 74HCT123. Bypass with a ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74HCT123DD
  • 74HCT123DPW
  • 74HCT123DBQ

CAD (KiCad official)

  • Symbol: 74HCT123D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (20 pp, sha256 0b5ba7a32cf4830a, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF