74HC273PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MR	input	Master reset input, active LOW. A LOW on MR asynchronously forces all eight Qn outputs LOW, overriding the clock and Dn inputs.
2	Q0	output	Flip-flop 0 output. Latches the state of D0 on the LOW-to-HIGH transition of CP; forced LOW when MR is LOW.
3	D0	input	Data input to flip-flop 0. Sampled on the rising edge of CP subject to setup and hold times.
4	D1	input	Data input to flip-flop 1. Sampled on the rising edge of CP.
5	Q1	output	Flip-flop 1 output. Latches D1 on the rising edge of CP; forced LOW when MR is LOW.
6	Q2	output	Flip-flop 2 output. Latches D2 on the rising edge of CP; forced LOW when MR is LOW.
7	D2	input	Data input to flip-flop 2. Sampled on the rising edge of CP.
8	D3	input	Data input to flip-flop 3. Sampled on the rising edge of CP.
9	Q3	output	Flip-flop 3 output. Latches D3 on the rising edge of CP; forced LOW when MR is LOW.
10	GND	power_in	Ground reference, 0 V.
11	CP	input	Clock input, positive-edge triggered. All eight flip-flops latch their Dn inputs on the LOW-to-HIGH transition of CP.
12	Q4	output	Flip-flop 4 output. Latches D4 on the rising edge of CP; forced LOW when MR is LOW.
13	D4	input	Data input to flip-flop 4. Sampled on the rising edge of CP.
14	D5	input	Data input to flip-flop 5. Sampled on the rising edge of CP.
15	Q5	output	Flip-flop 5 output. Latches D5 on the rising edge of CP; forced LOW when MR is LOW.
16	Q6	output	Flip-flop 6 output. Latches D6 on the rising edge of CP; forced LOW when MR is LOW.
17	D6	input	Data input to flip-flop 6. Sampled on the rising edge of CP.
18	D7	input	Data input to flip-flop 7. Sampled on the rising edge of CP.
19	Q7	output	Flip-flop 7 output. Latches D7 on the rising edge of CP; forced LOW when MR is LOW.
20	VCC	power_in	Supply voltage. 2.0 V to 6.0 V for 74HC273 (4.5 V to 5.5 V for 74HCT273).

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	TSSOP-20
Category	Logic
Pins	20

Ordering variants

Same part, different packaging or reel option.

74HC273PW
74HC273PWD
74HC273PWBQ

CAD (KiCad official)

Symbol: 74HC273PW
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (17 pp, sha256 dac5acf608742f73, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF