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74hc245pw-q100j
Public Unreviewedby Ray
Nexperia Buffer/Driver/Transceiver, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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markdown74HC245PW-Q100J
Nexperia · Buffer/Driver/Transceiver · TSSOP-20
74HC245PW-Q100J from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIR | input | Direction control input. When LOW, data flows from B bus to A bus (B->A). When HIGH, data flows from A bus to B bus (A->B). CMOS input levels referenced to VCC (2.0-6.0 V). |
| 2 | A0 | bidirectional | Bus A bit 0. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 3 | A1 | bidirectional | Bus A bit 1. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 4 | A2 | bidirectional | Bus A bit 2. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 5 | A3 | bidirectional | Bus A bit 3. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 6 | A4 | bidirectional | Bus A bit 4. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 7 | A5 | bidirectional | Bus A bit 5. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 8 | A6 | bidirectional | Bus A bit 6. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 9 | A7 | bidirectional | Bus A bit 7. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 10 | GND | power_in | Ground reference (0 V). Connect to system ground. |
| 11 | B7 | bidirectional | Bus B bit 7. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 12 | B6 | bidirectional | Bus B bit 6. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 13 | B5 | bidirectional | Bus B bit 5. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 14 | B4 | bidirectional | Bus B bit 4. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 15 | B3 | bidirectional | Bus B bit 3. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 16 | B2 | bidirectional | Bus B bit 2. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 17 | B1 | bidirectional | Bus B bit 1. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 18 | B0 | bidirectional | Bus B bit 0. Bidirectional 3-state I/O pin; direction set by DIR, high-impedance when OE is HIGH. |
| 19 | OE | input | Output enable input, active LOW. When LOW, transceiver is enabled and data flows in the direction set by DIR. When HIGH, both A and B ports are placed in the high-impedance OFF-state. |
| 20 | VCC | power_in | Positive supply voltage. Operating range 2.0-6.0 V for 74HC245-Q100 (CMOS levels). Absolute maximum -0.5 to +7 V. Decouple to GND close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Ordering variants
74HC245PW-Q100J74HC245PW-Q100J74HCT245PW-Q10074HC245PW-Q100J74HC245D-Q10074HC245PW-Q100J74HCT245D-Q10074HC245PW-Q100J74HC245BQ-Q10074HC245PW-Q100J74HCT245BQ-Q100
CAD (KiCad official)
- Symbol:
74HC245PW-Q100J - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (None pp, sha256
d440653b1177e397, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).