component
74hc02drg
Public Unreviewedby Ray
HANSCHIP semiconductor Gates, SOP-14L. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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markdown74HC02DRG
HANSCHIP semiconductor · Gates · SOP-14L
74HC02DRG from HANSCHIP semiconductor, in a SOP-14L. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | output | Output of NOR gate 1. Y1 = NOT(A1 + B1). CMOS push-pull output; drives up to 10 LSTTL loads with |
| 2 | A1 | input | A-input of NOR gate 1. High-impedance CMOS input (input leakage ≤ 1.0 µA). Unused inputs must be tied to GND or VCC. |
| 3 | B1 | input | B-input of NOR gate 1. High-impedance CMOS input (input leakage ≤ 1.0 µA). Unused inputs must be tied to GND or VCC. |
| 4 | Y2 | output | Output of NOR gate 2. Y2 = NOT(A2 + B2). CMOS push-pull output; drives up to 10 LSTTL loads with |
| 5 | A2 | input | A-input of NOR gate 2. High-impedance CMOS input (input leakage ≤ 1.0 µA). Unused inputs must be tied to GND or VCC. |
| 6 | B2 | input | B-input of NOR gate 2. High-impedance CMOS input (input leakage ≤ 1.0 µA). Unused inputs must be tied to GND or VCC. |
| 7 | GND | power_in | Ground reference (0 V). Return for VCC. Absolute max supply current between VCC and GND is 50 mA. |
| 8 | A3 | input | A-input of NOR gate 3. High-impedance CMOS input (input leakage ≤ 1.0 µA). Unused inputs must be tied to GND or VCC. |
| 9 | B3 | input | B-input of NOR gate 3. High-impedance CMOS input (input leakage ≤ 1.0 µA). Unused inputs must be tied to GND or VCC. |
| 10 | Y3 | output | Output of NOR gate 3. Y3 = NOT(A3 + B3). CMOS push-pull output; drives up to 10 LSTTL loads with |
| 11 | A4 | input | A-input of NOR gate 4. High-impedance CMOS input (input leakage ≤ 1.0 µA). Unused inputs must be tied to GND or VCC. |
| 12 | B4 | input | B-input of NOR gate 4. High-impedance CMOS input (input leakage ≤ 1.0 µA). Unused inputs must be tied to GND or VCC. |
| 13 | Y4 | output | Output of NOR gate 4. Y4 = NOT(A4 + B4). CMOS push-pull output; drives up to 10 LSTTL loads with |
| 14 | VCC | power_in | Positive supply voltage. Recommended operating range 2.0 V to 6.0 V (absolute max 7.0 V). Bypass with a 0.1 µF ceramic capacitor close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | SOP-14L |
| Category | Logic |
| Pins | 14 |
Ordering variants
74HC02DRG74HC02DRG474HC02DRGPG74HC02DRGPWRG
CAD (KiCad official)
- Symbol:
74HC02DRG - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14L (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HANSCHIP semiconductor datasheet (None pp, sha256
ea468ac442274032, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).