component
74HC00S
Public Unreviewedby Ray
GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Symbol & Footprint
Schematic Symbol
Open full view ↗PCB Footprint
Open full view ↗Datasheet
Open in new tab ↗README
markdown74HC00S
GR · Gates · SOP-14
74HC00S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Input A of NAND gate 1. CMOS logic input; VIH >= 4.2 V and VIL <= 1.8 V at VCC=6.0 V. Input current <= 1 uA. |
| 2 | B1 | input | Input B of NAND gate 1. CMOS logic input; VIH >= 4.2 V and VIL <= 1.8 V at VCC=6.0 V. Input current <= 1 uA. |
| 3 | Y1 | output | Output of NAND gate 1 (Y1 = NAND(A1,B1)). Push-pull CMOS output; |
| 4 | A2 | input | Input A of NAND gate 2. CMOS logic input; VIH >= 4.2 V and VIL <= 1.8 V at VCC=6.0 V. Input current <= 1 uA. |
| 5 | B2 | input | Input B of NAND gate 2. CMOS logic input; VIH >= 4.2 V and VIL <= 1.8 V at VCC=6.0 V. Input current <= 1 uA. |
| 6 | Y2 | output | Output of NAND gate 2 (Y2 = NAND(A2,B2)). Push-pull CMOS output; |
| 7 | GND | power_in | Ground reference (0 V). Common return for supply and logic signals; ICC (through VCC or GND) absolute max 50 mA. |
| 8 | Y3 | output | Output of NAND gate 3 (Y3 = NAND(A3,B3)). Push-pull CMOS output; |
| 9 | A3 | input | Input A of NAND gate 3. CMOS logic input; VIH >= 4.2 V and VIL <= 1.8 V at VCC=6.0 V. Input current <= 1 uA. |
| 10 | B3 | input | Input B of NAND gate 3. CMOS logic input; VIH >= 4.2 V and VIL <= 1.8 V at VCC=6.0 V. Input current <= 1 uA. |
| 11 | Y4 | output | Output of NAND gate 4 (Y4 = NAND(A4,B4)). Push-pull CMOS output; |
| 12 | A4 | input | Input A of NAND gate 4. CMOS logic input; VIH >= 4.2 V and VIL <= 1.8 V at VCC=6.0 V. Input current <= 1 uA. |
| 13 | B4 | input | Input B of NAND gate 4. CMOS logic input; VIH >= 4.2 V and VIL <= 1.8 V at VCC=6.0 V. Input current <= 1 uA. |
| 14 | VCC | power_in | Positive supply. Operating range 2.0-6.0 V (typ 5 V, absolute max 6.5 V). Bypass with a local 100 nF decoupling capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
74HC00SS74HC00SD
CAD (KiCad official)
- Symbol:
74HC00S - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (None pp, sha256
421c6ba2310c2c64, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).