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74AHCT240PW

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by Ray

Nexperia Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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74AHCT240PW

Nexperia · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

74AHCT240PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Bank 1 output enable, active LOW. Drive LOW to enable outputs 1Y0..1Y3; drive HIGH to force those outputs to high-impedance (Z). TTL/Schmitt-trigger input, VI up to 5.5 V (over-voltage tolerant).
2 1A0 input Bank 1 data input bit 0. Drives inverted output 1Y0 when 1OE is LOW. Schmitt-trigger, TTL-level, over-voltage tolerant input.
3 2Y0 tri_state Bank 2 data output bit 0. Inverted buffer of 2A0 when 2OE is LOW; high-impedance when 2OE is HIGH. IOH/IOL up to ±8 mA typical drive.
4 1A1 input Bank 1 data input bit 1. Drives inverted output 1Y1 when 1OE is LOW. Schmitt-trigger, TTL-level, over-voltage tolerant input.
5 2Y1 tri_state Bank 2 data output bit 1. Inverted buffer of 2A1 when 2OE is LOW; high-impedance when 2OE is HIGH.
6 1A2 input Bank 1 data input bit 2. Drives inverted output 1Y2 when 1OE is LOW. Schmitt-trigger, TTL-level, over-voltage tolerant input.
7 2Y2 tri_state Bank 2 data output bit 2. Inverted buffer of 2A2 when 2OE is LOW; high-impedance when 2OE is HIGH.
8 1A3 input Bank 1 data input bit 3. Drives inverted output 1Y3 when 1OE is LOW. Schmitt-trigger, TTL-level, over-voltage tolerant input.
9 2Y3 tri_state Bank 2 data output bit 3. Inverted buffer of 2A3 when 2OE is LOW; high-impedance when 2OE is HIGH.
10 GND power_in Ground reference (0 V). All voltages in the datasheet are referenced to GND.
11 2A3 input Bank 2 data input bit 3. Drives inverted output 2Y3 when 2OE is LOW. Schmitt-trigger, TTL-level, over-voltage tolerant input.
12 1Y3 tri_state Bank 1 data output bit 3. Inverted buffer of 1A3 when 1OE is LOW; high-impedance when 1OE is HIGH.
13 2A2 input Bank 2 data input bit 2. Drives inverted output 2Y2 when 2OE is LOW. Schmitt-trigger, TTL-level, over-voltage tolerant input.
14 1Y2 tri_state Bank 1 data output bit 2. Inverted buffer of 1A2 when 1OE is LOW; high-impedance when 1OE is HIGH.
15 2A1 input Bank 2 data input bit 1. Drives inverted output 2Y1 when 2OE is LOW. Schmitt-trigger, TTL-level, over-voltage tolerant input.
16 1Y1 tri_state Bank 1 data output bit 1. Inverted buffer of 1A1 when 1OE is LOW; high-impedance when 1OE is HIGH.
17 2A0 input Bank 2 data input bit 0. Drives inverted output 2Y0 when 2OE is LOW. Schmitt-trigger, TTL-level, over-voltage tolerant input.
18 1Y0 tri_state Bank 1 data output bit 0. Inverted buffer of 1A0 when 1OE is LOW; high-impedance when 1OE is HIGH.
19 2OE input Bank 2 output enable, active LOW. Drive LOW to enable outputs 2Y0..2Y3; drive HIGH to force those outputs to high-impedance (Z). TTL/Schmitt-trigger input, VI up to 5.5 V (over-voltage tolerant).
20 VCC power_in Positive supply. Recommended operating range 4.5 V to 5.5 V (TTL-compatible AHCT family); absolute max 7.0 V. Bypass locally to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • 74AHCT240PW
  • 74AHCT240PWD
  • 74AHCT240PWBQ

CAD (KiCad official)

  • Symbol: 74AHCT240PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 77bf3132ed98fa4c, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF