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Contents

README

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5V41236PGGI8

RENESAS · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-20

5V41236PGGI8 from RENESAS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDXD power_in +3.3V digital supply input. Decouple with 0.01 µF to GND (pin 9) as close to the pin as possible.
2 S0 input Spread spectrum select pin #0. Combined with S1/S2 selects spread% (-0.5, -1.0, -1.5, or none) and output frequency (100/200 MHz). Internal 100 kΩ pull-up.
3 S1 input Spread spectrum select pin #1. Combined with S0/S2 selects spread% and output frequency. Internal 100 kΩ pull-up.
4 S2 input Spread spectrum select pin #2. Combined with S0/S1 selects spread% and output frequency (S2=0 → 100 MHz, S2=1 → 200 MHz base). Internal 100 kΩ pull-up.
5 X1 input Crystal connection input. Connect to a 25 MHz fundamental-mode crystal or a clock input. Optional tuning cap to ground: (CL-12)×2 pF.
6 X2 output Crystal connection output. Connect to a 25 MHz fundamental-mode crystal, or leave open when X1 is driven by an external clock. Optional tuning cap to ground.
7 PD# input Active-low power-down. When low, powers down all PLLs and tri-states all outputs. Internal 100 kΩ pull-up.
8 OE input Output enable. High = enable outputs; Low = tri-state outputs. Internal 100 kΩ pull-up. Output enable/disable time ≤ 100 ns.
9 GNDXD power_in Digital ground return. Pair with VDDXD (pin 1) 0.01 µF decoupling capacitor.
10 IREF passive Current reference. Connect a precision resistor (e.g. 475 Ω 1% for 50 Ω trace impedance, giving IREF ≈ 2.32 mA) to ground. Output current IOH ≈ 6 × IREF.
11 CLKD# output Differential HCSL complement output of clock D. Selectable 100/200 MHz spread-spectrum clock, 0.7 V current-mode. Requires external series 33 Ω + 49.9 Ω to ground termination.
12 CLKD output Differential HCSL true output of clock D. Selectable 100/200 MHz spread-spectrum clock, 0.7 V current-mode.
13 CLKC# output Differential HCSL complement output of clock C. Selectable 100/200 MHz spread-spectrum clock, 0.7 V current-mode.
14 CLKC output Differential HCSL true output of clock C. Selectable 100/200 MHz spread-spectrum clock, 0.7 V current-mode.
15 VDDODA power_in +3.3V analog supply input. Decouple with 0.01 µF to GND (pin 16) as close to the pin as possible.
16 GNDODA power_in Analog ground return. Pair with VDDODA (pin 15) 0.01 µF decoupling capacitor.
17 CLKB# output Differential HCSL complement output of clock B. Selectable 100/200 MHz spread-spectrum clock, 0.7 V current-mode.
18 CLKB output Differential HCSL true output of clock B. Selectable 100/200 MHz spread-spectrum clock, 0.7 V current-mode.
19 CLKA# output Differential HCSL complement output of clock A. Selectable 100/200 MHz spread-spectrum clock, 0.7 V current-mode.
20 CLKA output Differential HCSL true output of clock A. Selectable 100/200 MHz spread-spectrum clock, 0.7 V current-mode.

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-20
Category Clock/Timing
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • 5V41236PGGI8
  • 5V41236PGGI8PGG8

CAD (KiCad official)

  • Symbol: 5V41236PGGI8
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (None pp, sha256 cd8eac429e30fcfc, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF