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InstaPCB vs JLCPCB
UnreviewedSide-by-side capability comparison: 4 h vs 5 d, 1-board MOQ, 0.08 mm traces, selective v-scoring, edge plating included.
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<header class="page">
<div class="eyebrow">PCB capability comparison</div>
<h1><span class="insta">InstaPCB</span><span class="vs">vs</span><span class="jlc">JLCPCB</span></h1>
<p class="subtitle">
InstaPCB is Adom's on-site UV-fiber-laser fab + solder-jet assembly line in Fort Worth, TX. JLCPCB is the high-volume Chinese prototype house most engineers benchmark against. The matrix below covers every spec a customer or DFM tool needs at quote time.
</p>
</header>
<div class="legend">
<span class="chip win">● InstaPCB advantage</span>
<span class="chip tie">● Tie / equivalent</span>
<span class="chip loss">● JLCPCB advantage</span>
<span class="chip derived">– – – derived from process physics (replace with authoritative)</span>
</div>
<main>
<table>
<thead class="sticky">
<tr>
<th>Parameter</th>
<th class="brand-insta">InstaPCB</th>
<th class="brand-jlc">JLCPCB (standard process)</th>
<th>InstaPCB advantage</th>
</tr>
</thead>
<tbody>
<!-- ============ HEADLINE ============ -->
<tr class="section-row"><td colspan="4"><span class="section-title">Headline — turnaround & MOQ</span></td></tr>
<tr class="row">
<td class="param">Turnaround (fab + assembly)</td>
<td class="val win"><span class="v">4 hours</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">3–5 days standard<br>24–48 h express</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">~30× faster end-to-end than JLCPCB express, ~30× faster than standard. Boards land in your cloud workcell within an afternoon.</td>
</tr>
<tr class="row">
<td class="param">Minimum order quantity</td>
<td class="val win"><span class="v">1 board</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">5 boards</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">Single-board ordering. No "burning" four extra boards every iteration — respin one, eat lunch, the next revision lands.</td>
</tr>
<tr class="row">
<td class="param">Component sourcing</td>
<td class="val win"><span class="v">Drone delivery from Mouser DFW (~40 min)</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">JLCPCB / LCSC stock (in-house)</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">Mouser carries ~10× more SKUs than LCSC at any given time. Drone delivery means you don't pre-order parts; the line orders them when your job hits the queue.</td>
</tr>
<!-- ============ MECHANICAL ============ -->
<tr class="section-row"><td colspan="4"><span class="section-title">Mechanical</span></td></tr>
<tr class="row">
<td class="param">Board thickness</td>
<td class="val loss"><span class="v">1.6 mm only</span><span class="src">authoritative</span></td>
<td class="val win"><span class="v">0.4 / 0.6 / 0.8 / 1.0 / 1.2 / 1.6 / 2.0 / 3.2 mm</span><span class="src">jlcpcb.com</span></td>
<td class="callout loss">JLCPCB wins on thickness flexibility. InstaPCB ships only the standard 1.6 mm FR4 stack today.</td>
</tr>
<tr class="row">
<td class="param">Layer count</td>
<td class="val loss"><span class="v">1, 2, 4, 6</span><span class="src">authoritative</span></td>
<td class="val win"><span class="v">1–20 (32 on advanced)</span><span class="src">jlcpcb.com</span></td>
<td class="callout loss">JLCPCB goes deeper for HDI / backplane work. InstaPCB targets the prototyping sweet spot at 1L–6L.</td>
</tr>
<tr class="row">
<td class="param">Min board size</td>
<td class="val tie"><span class="v derived" title="Derived — physical handling floor">5 × 5 mm</span><span class="src">derived</span></td>
<td class="val tie"><span class="v">5 × 5 mm</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tie at the bottom end.</td>
</tr>
<tr class="row">
<td class="param">Max board size</td>
<td class="val tie"><span class="v">304.8 × 381 mm (12" × 15")</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">400 × 500 mm</span><span class="src">jlcpcb.com</span></td>
<td class="callout">JLCPCB's bed is ~30% larger in each dimension, but InstaPCB's 12" × 15" envelope handles every standard PCB form factor (Eurocard, Mini-ITX, half-size SBC, motherboards up to ATX).</td>
</tr>
<tr class="row">
<td class="param">Panelization</td>
<td class="val win"><span class="v">Native single-board (depanel laser)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">V-cut / mouse-bite panelization required for <10 cm² boards</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">No panel-design overhead. The laser cuts the final outline as the last step (per aci-instapcb-process steps 23–25).</td>
</tr>
<tr class="row">
<td class="param">Selective V-scoring</td>
<td class="val win"><span class="v">Yes — any 2D curve with designer-placed trace bridges (0.5 mm top / 0.5 mm bottom ablation, 0.6 mm FR4 web)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">Not offered — straight V-cut only, no trace bridges</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">Adom invented this. Snap off curved daughtercards, test-fixture wings, irregular sub-modules with hand pressure. Mark segments as "no-ablate" bridges and traces stay live across the score — run programming + tests on the assembled board, then snap the wing off when you're done. Replaces mousebites entirely; resulting edge is clean and finished, no nibble residue.</td>
</tr>
<tr class="row">
<td class="param">Tooling holes / fiducials</td>
<td class="val win"><span class="v">Auto-burned at fab time</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">Auto-added if omitted</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">InstaPCB step 2 burns 3–4 fiducials per board before any other process. Designer never has to add them.</td>
</tr>
<tr class="row">
<td class="param">Castellated pads</td>
<td class="val tie"><span class="v derived">Supported (≥ 0.6 mm)</span><span class="src">derived</span></td>
<td class="val tie"><span class="v">Supported</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Both support castellation. InstaPCB's spec is laser-cut after via plating.</td>
</tr>
<tr class="row">
<td class="param">Edge plating</td>
<td class="val win"><span class="v">Supported on any edge</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">Supported (per-job add-on)</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">Free side-effect of the InstaPCB process: interior slots are laser-cut at the same step as the via drills, so their walls get electroplated alongside the barrels. Depanel cuts the remaining web and the plated slot interior becomes the finished board edge — no extra step, no add-on fee.</td>
</tr>
<!-- ============ CONDUCTOR ============ -->
<tr class="section-row"><td colspan="4"><span class="section-title">Conductor (copper)</span></td></tr>
<tr class="row">
<td class="param">Min trace width</td>
<td class="val win"><span class="v">0.08 mm (3 mil)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">0.127 mm (5 mil) on 2L<br>0.09 mm (3.5 mil) on 6L+</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">~36% finer trace than JLCPCB's standard 2-layer process. UV-fiber-laser ablation has a much tighter kerf than chemical etching.</td>
</tr>
<tr class="row">
<td class="param">Min trace spacing</td>
<td class="val win"><span class="v">0.08 mm (3 mil)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">0.127 mm (5 mil) on 2L</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">Same advantage as trace width — laser-direct removes the etch-undercut margin.</td>
</tr>
<tr class="row">
<td class="param">Trace-to-edge clearance</td>
<td class="val win"><span class="v">0.05 mm (2 mil)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">0.3 mm (12 mil)</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">6× tighter to the board edge. Mechanical routing leaves ragged FR4; laser depanel is glass-clean.</td>
</tr>
<tr class="row">
<td class="param">Copper weight</td>
<td class="val loss"><span class="v">0.5 oz (17.5 µm)</span><span class="src">authoritative</span></td>
<td class="val win"><span class="v">0.5 / 1 / 2 / 3 oz</span><span class="src">jlcpcb.com</span></td>
<td class="callout loss">JLCPCB wins for high-current / power-board work. InstaPCB's 0.5 oz is optimized for fine-pitch signal.</td>
</tr>
<tr class="row">
<td class="param">Plating thickness inside via barrel</td>
<td class="val tie"><span class="v derived">≈ 17.5 µm</span><span class="src">derived</span></td>
<td class="val tie"><span class="v">≈ 25 µm</span><span class="src">jlcpcb.com</span></td>
<td class="callout">JLCPCB plates a slightly thicker barrel; InstaPCB's electrolytic step matches the foil weight (0.5 oz).</td>
</tr>
<!-- ============ DRILLED ============ -->
<tr class="section-row"><td colspan="4"><span class="section-title">Drilled features</span></td></tr>
<tr class="row">
<td class="param">Min drill diameter (plated via)</td>
<td class="val win"><span class="v">0.20 mm (8 mil)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">0.30 mm (12 mil) on 2L<br>0.20 mm on 4L+</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">InstaPCB hits the JLCPCB-multilayer drill spec on a 2-layer board. UV laser drills don't bend or wear like mechanical drills.</td>
</tr>
<tr class="row">
<td class="param">Min annular ring (per side)</td>
<td class="val win"><span class="v">0.125 mm (5 mil)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">0.15 mm (6 mil)</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">25 µm tighter ring. Smaller via pad → more routing channels per chip.</td>
</tr>
<tr class="row">
<td class="param">Min outer pad on min drill</td>
<td class="val win"><span class="v">0.45 mm (drill + 0.25)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">0.60 mm (drill + 0.30) on 2L<br>0.45 mm on 4L+</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">Direct consequence of the smaller drill + tighter annular ring.</td>
</tr>
<tr class="row">
<td class="param">Min hole-to-hole spacing</td>
<td class="val tie"><span class="v">0.25 mm</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">0.25 mm</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied at the standard floor.</td>
</tr>
<tr class="row">
<td class="param">Min hole-to-edge clearance</td>
<td class="val tie"><span class="v">0.30 mm</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">0.30 mm</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied.</td>
</tr>
<tr class="row">
<td class="param">Max aspect ratio</td>
<td class="val loss"><span class="v derived">8 : 1</span><span class="src">derived</span></td>
<td class="val win"><span class="v">10 : 1</span><span class="src">jlcpcb.com</span></td>
<td class="callout loss">JLCPCB wins on deep-via work; InstaPCB's 1.6 mm × 0.2 mm minimum drill caps at 8:1.</td>
</tr>
<tr class="row">
<td class="param">Blind / buried vias</td>
<td class="val loss"><span class="v">Not offered</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">Not offered (standard process)</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied — both require advanced multi-step process not on either standard tier.</td>
</tr>
<!-- ============ MASK + SILK ============ -->
<tr class="section-row"><td colspan="4"><span class="section-title">Solder mask + silkscreen</span></td></tr>
<tr class="row">
<td class="param">Solder mask color</td>
<td class="val loss"><span class="v">Green only</span><span class="src">authoritative</span></td>
<td class="val win"><span class="v">Green / Blue / Red / Black / White / Purple / Yellow</span><span class="src">jlcpcb.com</span></td>
<td class="callout loss">JLCPCB wins on color choice. Adom's vacuum-laminated mask process is single-color today.</td>
</tr>
<tr class="row">
<td class="param">Solder mask web (sliver)</td>
<td class="val tie"><span class="v">0.10 mm</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">0.10 mm</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied — mask sliver is the same physical floor on both processes.</td>
</tr>
<tr class="row">
<td class="param">Solder mask expansion (per side)</td>
<td class="val tie"><span class="v derived">0.05 mm</span><span class="src">derived</span></td>
<td class="val tie"><span class="v">0.05 mm</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied.</td>
</tr>
<tr class="row">
<td class="param">Mask vs paste registration</td>
<td class="val win"><span class="v derived">±0.05 mm</span><span class="src">derived</span></td>
<td class="val loss"><span class="v">±0.075 mm typ.</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">UV laser positional accuracy beats stencil-aligned process at fine pitch.</td>
</tr>
<tr class="row">
<td class="param">Silkscreen process</td>
<td class="val tie"><span class="v">Laser-etched into mask (no ink)</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">White / black ink, screen-printed</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Trade-off — InstaPCB silk is matte etch (legible at zoom, lower contrast at distance). JLCPCB silk is high-contrast white-on-green ink.</td>
</tr>
<tr class="row">
<td class="param">Min silkscreen text height</td>
<td class="val win"><span class="v">0.10 mm (4 mil)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">1.0 mm (40 mil)</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">10× smaller text. Laser etch resolves much finer than printed silk — readable refdes on 0402 packages.</td>
</tr>
<tr class="row">
<td class="param">Min silkscreen stroke width</td>
<td class="val win"><span class="v derived">0.05 mm (2 mil)</span><span class="src">derived</span></td>
<td class="val loss"><span class="v">0.15 mm (6 mil)</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">3× tighter stroke. Same laser-kerf advantage as text height.</td>
</tr>
<tr class="row">
<td class="param">Silkscreen-to-pad clearance</td>
<td class="val tie"><span class="v">0.15 mm</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">0.15 mm</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied.</td>
</tr>
<!-- ============ FINISH ============ -->
<tr class="section-row"><td colspan="4"><span class="section-title">Surface finish + plating</span></td></tr>
<tr class="row">
<td class="param">Surface finish</td>
<td class="val loss"><span class="v derived">Bare-Cu / as-plated</span><span class="src">derived</span></td>
<td class="val win"><span class="v">HASL (Pb / Pb-free) / ENIG / OSP / immersion silver / tin</span><span class="src">jlcpcb.com</span></td>
<td class="callout loss">JLCPCB wins on finish flexibility. InstaPCB's bare-Cu is fine because boards go from line → workcell within hours; oxidation isn't yet a problem.</td>
</tr>
<tr class="row">
<td class="param">Lead-free RoHS</td>
<td class="val tie"><span class="v">Yes (no leaded solder on line)</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">Yes (lead-free options)</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied.</td>
</tr>
<!-- ============ STACKUP / IMPEDANCE ============ -->
<tr class="section-row"><td colspan="4"><span class="section-title">Stackup + impedance</span></td></tr>
<tr class="row">
<td class="param">Default 2L stackup</td>
<td class="val tie"><span class="v">Cu / FR4 1.6 mm / Cu</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">Cu / FR4 1.6 mm / Cu</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied.</td>
</tr>
<tr class="row">
<td class="param">4L / 6L dielectric stack</td>
<td class="val tie"><span class="v derived">Symmetric FR4 + prepreg (specifics TBD)</span><span class="src">derived</span></td>
<td class="val tie"><span class="v">Symmetric FR4 + prepreg, multiple stacks published</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied at this level of detail. Authoritative InstaPCB 4L/6L stack docs forthcoming.</td>
</tr>
<tr class="row">
<td class="param">Impedance control</td>
<td class="val loss"><span class="v derived">Not offered at this tier</span><span class="src">derived</span></td>
<td class="val win"><span class="v">±10% (microstrip / coplanar / diff-pair)</span><span class="src">jlcpcb.com</span></td>
<td class="callout loss">JLCPCB wins for controlled-impedance work. InstaPCB's prototyping focus doesn't yet include impedance certification.</td>
</tr>
<!-- ============ ASSEMBLY ============ -->
<tr class="section-row"><td colspan="4"><span class="section-title">Assembly DFM</span></td></tr>
<tr class="row">
<td class="param">Solder application</td>
<td class="val win"><span class="v">Stencil-free piezo solder-jet (300 µm dome)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">Stainless steel laser-cut stencil + reflow</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">No stencil to design, manufacture, or store. Per-pad dispense means dot count scales with pad geometry, not stencil aperture rules.</td>
</tr>
<tr class="row">
<td class="param">Min pad-edge to pad-edge spacing</td>
<td class="val tie"><span class="v">0.30 mm (300 µm dot oversplatter rule)</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">0.20 mm (stencil aperture)</span><span class="src">jlcpcb.com</span></td>
<td class="callout">JLCPCB stencils can target tighter pad gaps; InstaPCB's solder-jet has alternating-dot fallback below the 300 µm rule.</td>
</tr>
<tr class="row">
<td class="param">BGA min pitch</td>
<td class="val tie"><span class="v">0.40 mm (alt-dot below)</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">0.40 mm (standard)</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied at standard tier.</td>
</tr>
<tr class="row">
<td class="param">Min pad width for clean joint</td>
<td class="val tie"><span class="v">0.35 mm (350 µm)</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">0.30 mm</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Roughly tied — InstaPCB's floor is set by the 300 µm dot + ±25 µm placement margin.</td>
</tr>
<tr class="row">
<td class="param">Adom-default passive size</td>
<td class="val win"><span class="v">0402</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">0603 (recommended) / 0402 supported</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">4-hour respin replaces hand-rework — kills the traditional argument for 0603. See electrical-engineering §4a.</td>
</tr>
<tr class="row">
<td class="param">DNP / placement-skip handling</td>
<td class="val tie"><span class="v">Excluded from BOM + dispense</span><span class="src">authoritative</span></td>
<td class="val tie"><span class="v">Excluded via DNP column in CPL</span><span class="src">jlcpcb.com</span></td>
<td class="callout">Tied.</td>
</tr>
<tr class="row">
<td class="param">In-line electrical test</td>
<td class="val win"><span class="v">Per-net probe (top + bottom layer, 26-step process steps 11 + 13)</span><span class="src">authoritative</span></td>
<td class="val loss"><span class="v">Visual + AOI standard; flying-probe optional add-on</span><span class="src">jlcpcb.com</span></td>
<td class="callout win">Every net probed before mask + silk. Catches shorts / opens before they leave the line.</td>
</tr>
</tbody>
</table>
</main>
<footer class="page">
<span>Last verified: <span class="pill">2026-05-07</span> — JLCPCB capabilities pulled from <a href="https://jlcpcb.com/capabilities/pcb-capabilities" target="_blank" rel="noopener">jlcpcb.com</a> and <a href="https://www.schemalyzer.com/en/blog/manufacturing/jlcpcb/jlcpcb-design-rules" target="_blank" rel="noopener">schemalyzer (late 2025 snapshot)</a>.</span>
<span>Source of truth: <a href="https://wiki-ufypy5dpx93o.adom.cloud/skills/instapcb" target="_blank" rel="noopener">instapcb skill</a> · gallia/skills/instapcb/SKILL.md</span>
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