BQ7692003PWR — BQ76920 3–5 Cell Li-Ion Battery Monitor AFE (I²C 0x08, 3.3 V LDO, CRC)

{
  "schema_version": 1,
  "type": "component",
  "slug": "bq7692003pwr",
  "title": "BQ7692003PWR — BQ76920 3–5 Cell Li-Ion Battery Monitor AFE (I²C 0x08, 3.3 V LDO, CRC)",
  "brief": "TI BQ76920 variant (BQ7692003PWR): 3-to-5-series cell battery monitor / AFE in 20-TSSOP, factory-configured for I²C address 0x08, 3.3 V REGOUT, and I²C CRC. Integrated 14-bit cell ADC, 16-bit coulomb",
  "version": "1.0.1",
  "tags": [],
  "license": "MIT",
  "component": {
    "mpn": "BQ7692003PWR — BQ76920 3–5 Cell Li-Ion Battery Monitor AFE (I²C 0x08, 3.3 V LDO, CRC)",
    "manufacturer": "Texas Instruments",
    "package": "20-TSSOP (PW)",
    "pin_count": 20,
    "category": "Battery Monitor / AFE",
    "subcategory": "",
    "body_size": null,
    "parts": {},
    "distributor_links": {}
  },
  "readme": "**Source:** [Texas Instruments — BQ769x0 3-Series to 15-Series Cell Battery Monitor Family (SLUSBK2I)](https://www.ti.com/lit/ds/symlink/bq76920.pdf)\n**Manufacturer:** Texas Instruments\n**Part Number:** BQ7692003PWR\n**Family:** BQ76920 / BQ76930 / BQ76940\n**Document:** SLUSBK2I — October 2013, Revised March 2022 (67 pages)\n**Package:** 20-TSSOP (PW), 6.5 mm × 4.4 mm × 1.2 mm\n**I²C Address:** 0x08 (7-bit)\n**LDO:** 3.3 V\n**CRC:** Yes\n\n## Description\n\nThe BQ7692003PWR is a factory-preconfigured orderable variant of the **Texas Instruments BQ76920**, a 3-to-5-series-cell analog front-end (AFE) for lithium-ion and lithium-iron-phosphate battery pack monitoring and protection. It is part of the broader BQ769x0 family — BQ76920 (3–5 cells, 20-TSSOP), BQ76930 (6–10 cells, 30-TSSOP), and BQ76940 (9–15 cells, 44-TSSOP) — all sharing the same register map and digital interface.\n\nThe BQ7692003PWR variant is factory-programmed with **I²C address 0x08**, a **3.3 V REGOUT LDO**, and **I²C CRC enabled**, shipped in tape-and-reel. No EEPROM programming is required.\n\nTypical applications include light electric vehicles (eBikes, eScooters, pedelecs), power tools and garden tools, battery backup units (BBU), energy storage systems (ESS), UPS systems, and other ≥10-cell industrial battery packs (where a BQ76940 would be the right family member).\n\nThe device integrates cell voltage measurement, pack current measurement (coulomb counter), internal die temperature plus up to three external thermistor inputs, hardware overcurrent / short-circuit / overvoltage / undervoltage protection with configurable thresholds, charge and discharge low-side NCH FET drivers, and cell balancing FETs. A host microcontroller drives the pack-management logic over I²C; an ALERT interrupt line signals protection events and ADC-ready conditions.\n\n## Key Specifications\n\n| Parameter | Value |\n| --- | --- |\n| Cells Supported | 3 to 5 (BQ76920 family) |\n| Supply Voltage (V_BAT) | 6 V to 25 V |\n| Absolute Max Supply | 36 V (BQ76920); up to 108 V per-pin rating within family |\n| LDO Output (REGOUT) | 3.3 V |\n| I²C Address | 0x08 (7-bit) |\n| I²C CRC | Enabled |\n| I²C Clock Frequency | up to 100 kHz |\n| Cell ADC Resolution | 14-bit |\n| Cell ADC LSB | 382 µV |\n| Coulomb Counter ADC | 16-bit, 8.44 µV LSB |\n| Thermistor Inputs | 3 (103AT) |\n| Protection Hardware | OV, UV, OCD, SCD |\n| Cell Balancing | Integrated FETs per cell |\n| FET Drivers | Low-side NCH CHG + DSG |\n| Package | 20-TSSOP (PW), 6.5 × 4.4 × 1.2 mm |\n| Operating Temperature | −40 °C to +85 °C |\n| Startup Current (SHIP mode) | 0.6 µA typ |\n\n## Features\n\n- Analog front-end for 3-to-5-series Li-ion / LiFePO₄ battery packs\n- Pure digital interface (I²C with optional CRC)\n- 14-bit internal ADC for cell voltage, die temperature, and external thermistor\n- Separate 16-bit coulomb-counter ADC for pack current\n- Direct support for up to three 103AT thermistors\n- Hardware overcurrent in discharge (OCD), short-circuit in discharge (SCD), overvoltage (OV), and undervoltage (UV) protections\n- Secondary-protector fault detection input\n- Integrated cell-balancing FETs (one per cell)\n- Low-side NCH CHG and DSG FET drivers\n- Alert interrupt line to host MCU (ALERT pin, open-drain)\n- 3.3 V REGOUT LDO with external pass FET option (REGSRC)\n- No EEPROM programming required — device is factory-preconfigured\n- High-voltage absolute-maximum supply rating (up to 108 V, family-dependent)\n- Random cell-connection order tolerant during pack assembly\n- SHIP mode for ultra-low-power storage (0.6 µA typical)\n\n## Pin Configuration\n\n| Pin | Name | Type | Description |\n| --- | --- | --- | --- |\n| 1 | DSG | O | Discharge FET driver (low-side NCH) |\n| 2 | CHG | O | Charge FET driver (low-side NCH) |\n| 3 | VSS | — | Chip VSS / device ground |\n| 4 | SDA | I/O | I²C data |\n| 5 | SCL | I | I²C clock |\n| 6 | TS1 | I | Thermistor #1 positive terminal (pull to VSS via 10 kΩ if unused) |\n| 7 | CAP1 | O | Capacitor to VSS (internal bias decoupling) |\n| 8 | REGOUT | P | Output LDO (3.3 V in this variant) |\n| 9 | REGSRC | I | Input source for output LDO |\n| 10 | BAT | P | Battery top-most terminal (supply pin) |\n| 11 | NC | — | No connect |\n| 12 | VC5 | I | Sense voltage, 5th cell positive terminal |\n| 13 | VC4 | I | Sense voltage, 4th cell positive terminal |\n| 14 | VC3 | I | Sense voltage, 3rd cell positive terminal |\n| 15 | VC2 | I | Sense voltage, 2nd cell positive terminal |\n| 16 | VC1 | I | Sense voltage, 1st cell positive terminal |\n| 17 | VC0 | I | Sense voltage, 1st cell negative terminal |\n| 18 | SRP | I | Current-sense resistor, side nearest VSS |\n| 19 | SRN | I | Current-sense resistor, positive side |\n| 20 | ALERT | I/O | Alert output / override input (open-drain) |\n\n## Absolute Maximum Ratings\n\nOver-operating free-air temperature range unless otherwise noted. Stresses beyond these ratings may cause permanent damage.\n\n| Parameter | Min | Max | Unit |\n| --- | --- | --- | --- |\n| V_BAT (BAT − VSS) | −0.3 | 36 | V |\n| V_I (VC0 − VSS) where n = 1..5 | −0.3 | (n × 7.2) | V |\n| V_I (SRN, SRP, SCL, SDA) | −0.3 | 9 | V |\n| V_I (VC0 − VC5x, CAP1 − VC5x, CAP1 − VSS, TS2 − VC5x, TS1 − VSS)² | −0.3 | 3.6 | V |\n| V_I (REGSRC) | −0.3 | 36 | V |\n| V_O (REGOUT, ALERT) | −0.3 | 36 | V |\n| V_O (DSG) | −0.3 | 20 | V |\n| V_O (CHG) | −0.3 | V_CHG,CLAMP | V |\n| I_CB Cell-balancing current (per cell) | — | 70 | mA |\n| I_DD Discharge pin input current when disabled | — | 7 | mA |\n| T_stg Storage temperature | −65 | 150 | °C |\n| T_SOL Lead temperature (soldering, 10 s) | — | 300 | °C |\n\n## Recommended Operating Conditions\n\nOver-operating free-air temperature range unless otherwise noted. All voltages relative to VSS.\n\n| Parameter | Min | Typ | Max | Unit |\n| --- | --- | --- | --- | --- |\n| V_BAT Supply voltage (BAT − VSS) | 6 | — | 25 | V |\n| V_BAT Cell-input differential (VC_n − VC_n−1) | 2 | — | 5 | V |\n| V_IN (VC0 − VSS) | 0 | — | 5 × n | V |\n| V_IN (TS1 − VSS) | −10 | — | 10 | mV |\n| V_IN (SRN) | −200 | — | 200 | mV |\n| V_OUT (CAP1 − VSS) | 0 | — | 3.6 | V |\n| V_OUT (REGOUT) | 0 | — | 16 | V |\n| I_CB Cell balancing current (internal per cell) | 0 | — | 50 | mA |\n| R_C External cell filter resistance | 40 | 100 | 1 K | Ω |\n| R_S Sense resistor filter resistance | 40 | 100 | 1 K | Ω |\n| C_C External cell input capacitance | 0.1 | 1 | 10 | µF |\n| C_T External supply filter capacitance | 40 | 100 | 1 K | µF |\n| C_F External sense filter capacitance | 1 | 10 | 40 | µF |\n| R_FILT Sense resistor filter resistance | 100 | 1 K | — | Ω |\n| R_ALERT ALERT pin to VSS resistor | — | 1 M | — | Ω |\n| C_L REGOUT loading capacitance | 1 | 4.7 | — | µF |\n| C_CAP REGSRC, CAP1, CAP2 and CAP3 output capacitance | 1 | — | — | µF |\n| R_TS External thermistor nominal resistance (103AT at 25 °C) | — | 10 K | — | Ω |\n| T_OPR Operating free-air temperature | −40 | — | 85 | °C |\n\n## Electrical Characteristics\n\nTypical conditions: T_A = 25 °C, BAT = 18 V (BQ76920) / 36 V (BQ76930) / 48 V (BQ76940), VCC = 4 V. Min/max apply over −40 °C to +85 °C unless noted.\n\n### Supply currents\n\n| Parameter | Test Condition | Min | Typ | Max | Unit |\n| --- | --- | --- | --- | --- | --- |\n| I_DD Normal mode, ADC off, CC off | Sum of I_CC,BAT and I_CC,REGSRC | — | 40 | 60 | µA |\n| I_DD Normal mode, ADC on, CC off | | — | 60 | 90 | µA |\n| I_DD Normal mode, ADC off, CC on | | — | 110 | 165 | µA |\n| I_DD Normal mode, ADC on, CC on | | — | 130 | 195 | µA |\n| I_CC,BAT Normal mode, ADC off | Into BAT pin | — | 30 | 45 | µA |\n| I_CC,BAT Normal mode, ADC on | | — | 50 | 75 | µA |\n| I_CC,REGSRC Normal mode, CC off | Into REGSRC pin | — | 10 | 15 | µA |\n| I_CC,REGSRC Normal mode, CC on | | — | 80 | 120 | µA |\n| I_SHIP SHIP/SHUTDOWN mode | Device in full shutdown, only VSTUP/BG and BOOT detector on | — | 0.6 | 1.8 | µA |\n\n### Cell voltage measurement\n\n| Parameter | Test Condition | Min | Typ | Max | Unit |\n| --- | --- | --- | --- | --- | --- |\n| ADC range | V_CELL measurements | 2 | — | 5 | V |\n| ADC LSB value | | — | 382 | — | µV |\n| ADC accuracy at 25 °C | V_CELL = 2.0 V to 5.0 V | — | ±25 | — | mV |\n| ADC accuracy 0 °C to 60 °C | V_CELL = 2.0 V to 5.0 V | — | ±25 | — | mV |\n| ADC accuracy −40 °C to 85 °C | V_CELL = 2.0 V to 5.0 V | −50 | ±35 | 50 | mV |\n\n### Coulomb-counter current measurement\n\n| Parameter | Test Condition | Min | Typ | Max | Unit |\n| --- | --- | --- | --- | --- | --- |\n| CC input range | | −200 | — | 200 | mV |\n| CC full scale | | −270 | — | 270 | mV |\n| CC LSB | | — | 8.44 | — | µV |\n| CC conversion time | Single conversion | — | 250 | — | ms |\n| Integral non-linearity | 16-bit fit over input voltage range ±200 mV | — | ±2 | ±40 | LSB |\n| Offset error | | — | ±1 | ±3 | LSB |\n| Gain error | Over input voltage range | −0.5 | — | +0.5 | % FSR |\n| Gain error drift | | — | — | ±150 | PPM/°C |\n| Effective input resistance | | 2.5 | — | — | MΩ |\n\n### Voltage protections (OV / UV / OCD / SCD)\n\n| Parameter | Test Condition | Min | Typ | Max | Unit |\n| --- | --- | --- | --- | --- | --- |\n| OV_RANGE | OV threshold range | 0x2008 | — | 0x2FFE | ADC |\n| UV_RANGE | UV threshold range | 0x1000 | — | 0x1FF0 | ADC |\n| OV_SYSTEP | OV and UV threshold step size | — | 16 | — | LSB |\n| UV_MNDUAL | UV minimum value to qualify | — | 0x0518 | — | ADC |\n| OV_DELAY | OV delay time options | 1 s / 2 s / 4 s / 8 s | | | |\n| UV_DELAY | UV delay time options | 1 s / 4 s / 8 s / 16 s | | | |\n| OCD_RANGE | OCD threshold range | 8 | — | 100 | mV |\n| OCD_STEP | OCD threshold step size | — | 2.78 / 5.56 | — | mV |\n| OCD_DELAY | Delay options | 8 / 22 / 200 / 1280 | | | ms |\n| SCD_RANGE | SCD threshold range | 22 | — | 200 | mV |\n| SCD_STEP | Step size | 11.1 / 22.2 | | | mV |\n| SCD_DELAY | Delay options | 35 / 50 / 70 / 100 / 140 / 200 / 280 / 400 | | | µs |\n\n## Thermal Information\n\n| Thermal Metric | BQ76920 (20-TSSOP PW) | BQ76930 (30-TSSOP DBT) | BQ76940 (44-TSSOP DBT) | Unit |\n| --- | --- | --- | --- | --- |\n| R_θJA Junction-to-ambient thermal resistance | 93.7 | 86.5 | 79.1 | °C/W |\n| R_θJC(top) Junction-to-case (top) | 28.7 | 19.4 | 17.5 | °C/W |\n| R_θJB Junction-to-board | 44.6 | 41.3 | 33.9 | °C/W |\n| ψ_JT Junction-to-top characterization | 1.3 | 0.5 | 0.5 | °C/W |\n| ψ_JB Junction-to-board characterization | 44.1 | 40.6 | 33.4 | °C/W |\n\n## Timing Requirements\n\nI²C-compatible interface. Typical conditions: T_A = 25 °C.\n\n| Parameter | Min | Typ | Max | Unit |\n| --- | --- | --- | --- | --- |\n| V_IL Input low logic threshold | — | — | REGOUT × 0.25 | V |\n| V_IH Input high logic threshold | REGOUT × 0.75 | — | — | V |\n| V_OL Output low logic drive | — | — | 0.20 | V |\n| t_r SCL, SDA fall time | — | — | 0.40 | µs |\n| V_OH Output high logic drive (not applicable due to open-drain) | N/A | N/A | N/A | V |\n| t_HIGH SCL pulse width high | 4.0 | — | — | µs |\n| t_LOW SCL pulse width low | 4.7 | — | — | µs |\n| t_SU,STA Setup time for START condition | 4.7 | — | — | µs |\n| t_HD,STA START condition hold time after first clock pulse is generated | 4.0 | — | — | µs |\n| t_SU,DAT Data setup time | 250 | — | — | ns |\n| t_HD,DAT Data hold time | 0 | — | — | µs |\n| t_SU,STO Setup time for STOP condition | 4.0 | — | — | µs |\n| t_BUF Bus free time between new transmission can start | 4.7 | — | — | µs |\n| t_HD,DAT Data out hold time after clock low | 0 | — | — | µs |\n| t_VD,DAT Data out valid time after clock low | — | — | 900 | ns |\n| f_SCL Clock frequency | 0 | — | 100 | kHz |\n\n## Packages\n\n| Part Number (T&R) | Family Variant | Cells | I²C Addr | LDO | CRC | Package |\n| --- | --- | --- | --- | --- | --- | --- |\n| BQ7692000PWR | BQ76920 | 3–5 | 0x08 | 2.5 V | No | 20-TSSOP (PW) |\n| BQ7692001PWR | BQ76920 | 3–5 | 0x08 | 2.5 V | Yes | 20-TSSOP (PW) |\n| BQ7692002PWR | BQ76920 | 3–5 | 0x08 | 3.3 V | No | 20-TSSOP (PW) |\n| **BQ7692003PWR** | **BQ76920** | **3–5** | **0x08** | **3.3 V** | **Yes** | **20-TSSOP (PW)** |\n| BQ7692006PWR | BQ76920 | 3–5 | 0x18 | 3.3 V | No | 20-TSSOP (PW) |\n| BQ7693000DBTR | BQ76930 | 6–10 | 0x08 | 2.5 V | No | 30-TSSOP (DBT) |\n| BQ7693003DBTR | BQ76930 | 6–10 | 0x08 | 3.3 V | Yes | 30-TSSOP (DBT) |\n| BQ7694000DBTR | BQ76940 | 9–15 | 0x08 | 2.5 V | No | 44-TSSOP (DBT) |\n| BQ7694003DBTR | BQ76940 | 9–15 | 0x08 | 3.3 V | Yes | 44-TSSOP (DBT) |\n\nPackage dimensions:\n\n| Package | Pins | Body Size |\n| --- | --- | --- |\n| TSSOP (PW) | 20 | 6.50 mm × 4.40 mm × 1.20 mm |\n| TSSOP (DBT) | 30 | 7.80 mm × 4.40 mm × 1.20 mm |\n| TSSOP (DBT) | 44 | 11.00 mm × 4.40 mm × 1.20 mm |\n\n## Applications\n\n- Light electric vehicles (LEV): eBikes, eScooters, pedelecs, pedal-assist bicycles\n- Power tools and garden tools\n- Battery backup units (BBU), energy storage systems (ESS), uninterruptible power supply (UPS) systems\n- Industrial battery packs (3-cell and up; use BQ76930/BQ76940 for ≥6-cell packs)\n\n## Communication Interface\n\nThe BQ7692003PWR variant communicates via I²C at the fixed 7-bit address **0x08**, with **CRC enabled** on every register read and write. The slave address is factory-set — this variant cannot be changed to 0x18 at runtime; use the BQ7692006PWR variant if a 0x18 address is required.\n\nRegister map spans 0x00–0x3B, covering:\n- System status (SYS_STAT) and ALERT mask (SYS_CTRL1/2)\n- OV / UV / SCD / OCD protection thresholds and delay settings\n- Cell voltages VC1..VC5 (14-bit, 382 µV LSB)\n- Coulomb-counter current (16-bit, 8.44 µV LSB) — paired with sense resistor R_SNS\n- Temperature sensor channels\n- Cell balancing enable per cell (CELLBAL1)\n- I²C CRC control\n\n## Key Formulas\n\n### Cell voltage ADC conversion\n\n$$V_{CELL} = ADC_{GAIN} \\times ADC_{CODE} + ADC_{OFFSET}$$\n\nwhere ADC_GAIN ≈ 382 µV/LSB and ADC_OFFSET is read from ADCOFFSET register (signed mV).\n\n### Coulomb-counter current\n\n$$I_{PACK} = \\frac{CC_{CODE} \\times 8.44\\ \\mu V}{R_{SNS}}$$\n\nwhere R_SNS is the external sense resistor (typically 1–10 mΩ).\n\n### OCD and SCD thresholds\n\n$$V_{OCD} = OCD_{RANGE_{LSB}} \\times OCD_{STEP}$$\n\n$$V_{SCD} = SCD_{RANGE_{LSB}} \\times SCD_{STEP}$$\n\nTrip current is then V_threshold / R_SNS.\n\n## Troubleshooting\n\n| Symptom | Cause | Fix |\n| --- | --- | --- |\n| Device does not respond on I²C | Incorrect address or CRC setting for the variant | BQ7692003PWR uses address 0x08 with CRC enabled — all reads/writes must include CRC byte |\n| ADC readings drift with temperature | Thermistor TS1 floating or filter caps wrong | Pull TS1 to VSS through 10 kΩ if unused; verify C_C per recommended operating conditions |\n| FET drivers not engaging | CHG/DSG disabled via SYS_CTRL2 or protection fault latched | Read SYS_STAT; clear latched protection bits by writing 1 to the corresponding SYS_STAT bit |\n| Coulomb counter reads 0 | CC not enabled | Set CC_EN in SYS_CTRL2; allow one 250 ms conversion cycle |\n| Large pack parasitic impedance causes voltage errors | Input cap grounding runs across sense resistor | Route cell input caps to local ground between battery tab and sense resistor (see layout example in datasheet §11) |\n",
  "author": {
    "id": "695820315b5f1e4db2fcf602",
    "name": "Kyle Bergstedt",
    "email": "[email protected]"
  },
  "visibility": {
    "public": true
  },
  "hero": null,
  "sample_prompts": [],
  "discovery_triggers": [],
  "discovery_pitch": null,
  "metadata": {},
  "created_at": "2026-05-28T05:31:08.054Z",
  "updated_at": "2026-05-28T05:31:08.054Z"
}