component
ZD24C128A-SSGMT
Public Unreviewedby Ray
Zetta EEPROM, SOP-8-150mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownZD24C128A-SSGMT
Zetta · EEPROM · SOP-8-150mil
ZD24C128A-SSGMT from Zetta, in a SOP-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device Address Input bit 0. Hard-wired to VCC or GND to set the least-significant hardware slave address bit; up to eight devices can share the I2C bus. Corresponds to the fifth bit of the I2C 7-bit slave address (device type identifier is 1010). |
| 2 | A1 | input | Device Address Input bit 1. Tie to VCC or GND to set the hardware slave-address bit. Combined with A0/A2 to distinguish up to eight EEPROMs on the same I2C bus. |
| 3 | A2 | input | Device Address Input bit 2. Tie to VCC or GND to set the most-significant hardware slave-address bit. Datasheet notes A2 corresponds to the fifth bit of the 7-bit I2C slave address. |
| 4 | GND | power_in | Ground reference for the power supply. Must be connected to the system ground (0 V). |
| 5 | SDA | bidirectional | Serial Data. Open-drain bidirectional I2C data line used to serially transfer data to and from the device. Requires an external pull-up resistor (<=10 kOhm); may be wire-ORed with other open-drain pins on the same bus. |
| 6 | SCL | input | Serial Clock. I2C clock input from the bus master. Input data on SDA is latched on the rising edge of SCL and output data is clocked out on the falling edge. Must be pulled high externally when the bus is idle. |
| 7 | WP | input | Write Protect (active high). Tie to GND for normal write operation; tie to VCC to inhibit all writes to the memory array. If left floating, an internal weak pull-down biases it toward GND, but Zetta recommends driving it to a known state. |
| 8 | VCC | power_in | Device power supply. Operating range 1.7 V to 5.5 V (2.5 V to 5.5 V required for 1 MHz Fast Mode Plus). Operation outside the valid VCC range may produce spurious results and should not be attempted. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Zetta |
| Package | SOP-8-150mil |
| Category | Memory |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
ZD24C128A-SSGMT
CAD (KiCad official)
- Symbol:
ZD24C128A-SSGMT - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8-150mil (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
zd24c128a-ssgmt.step |
122 KB | You want the bare part, or you mark your own boards. |
zd24c128a-ssgmt-etched.step |
2.8 MB | You want the part with ZD24C128A-SSGMT already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 691 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Zetta datasheet (28 pp, sha256
09f06e678ee0a7d7, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).