component
AD5227BUJZ10-RL7
Public Made by Adomby adom
Analog Devices Digital Potentiometers, TSOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5227BUJZ10-RL7
Analog Devices · Digital Potentiometers · TSOT-23-8
AD5227BUJZ10-RL7 from Analog Devices, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLK | input | Clock input: each clock pulse steps the wiper up or down per the U/D pin, it is negative-edge triggered, and the logic high level may be higher than VDD but must be lower than 5.5 V. |
| 2 | U/D | input | Up/down selection: logic 1 selects up and logic 0 selects down, and U can be higher than VDD but must be lower than 5.5 V. |
| 3 | A | passive | Resistor terminal A, with GND ≤ VA ≤ VDD. |
| 4 | GND | power_in | Common ground. |
| 5 | W | passive | Wiper terminal W, with GND ≤ VW ≤ VDD. |
| 6 | B | passive | Resistor terminal B, with GND ≤ VB ≤ VDD. |
| 7 | CS | input | Active-low chip select; when enabled the device steps on CLK, and the logic high level may be higher than VDD but must be lower than 5.5 V. |
| 8 | VDD | power_in | Positive power supply, 2.7 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSOT-23-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| R-DNL Resistor Differential Nonlinearity | R-DNL | -0.5 | 0.15 | 0.5 | LSB | RWB, A = no connect | 3 |
| R-INL Resistor Integral Nonlinearity | R-INL | -1 | 0.3 | 1 | LSB | RWB, A = no connect | 3 |
| Nominal Resistor Tolerance | ΔRAB/RAB | -20 | 20 | % | 3 | ||
| Wiper Resistance | RW | 100 | 250 | Ω | VDD = 2.7 V | 3 | |
| Wiper Resistance | RW | 50 | 200 | Ω | VDD = 2.8 V to 5.5 V | 3 | |
| Integral Nonlinearity | INL | -1 | 0.1 | 1 | LSB | 3 | |
| Differential Nonlinearity | DNL | -0.5 | 0.1 | 0.5 | LSB | 3 | |
| Full-Scale Error | VWFSE | -1.2 | -0.5 | 0 | LSB | ≥+31 steps from midscale | 3 |
| Full-Scale Error | VWFSE | -1 | -0.5 | 0 | LSB | −40°C < TA < +60°C, VDD = 2.8 V to 5.5 V | 3 |
| Zero-Scale Error | VWZSE | 0 | 0.5 | 1.2 | LSB | ≤−32 steps from midscale | 3 |
| Zero-Scale Error | VWZSE | 0 | 0.5 | 1 | LSB | −40°C < TA < +60°C, VDD = 2.8 V to 5.5 V | 3 |
| Voltage Range (resistor terminals) | VA, VB, VW | 0 | V | With respect to GND | 3 | ||
| Common-Mode Leakage | ICM | 1 | nA | VA = VB = VW | 3 | ||
| Input Logic High | VIH | 2.4 | 5.5 | V | 3 | ||
| Input Logic Low | VIL | 0 | 0.8 | V | 3 | ||
| Input Current | II | -1 | 1 | μA | VIN = 0 V or 5 V | 3 | |
| Power Supply Range | VDD | 2.7 | 5.5 | V | 3 | ||
| Supply Current | IDD | 0.4 | 3 | μA | VIH = 5 V or VIL = 0 V, VDD = 5 V | 3 | |
| Power Supply Sensitivity | PSSR | 0.01 | 0.05 | %/% | VDD = 5 V ± 10% | 3 | |
| Clock Frequency | fCLK | 50 | MHz | 4 | |||
| Input Clock Pulse Width | tCH, tCL | 10 | ns | Clock level high or low | 4 | ||
| CS to CLK Setup Time | tCSS | 10 | ns | 4 | |||
| CS Rise to CLK Hold Time | tCSH | 10 | ns | 4 | |||
| U/D to Clock Fall Setup Time | tUDS | 10 | ns | 4 | |||
| VDD to GND | VDD | -0.3 | 7 | V | 5 | ||
| VA, VB, VW to GND | VA, VB, VW | 0 | V | 5 | |||
| Digital Input Voltage to GND (CS, CLK, U/D) | VIN | 0 | V | 5 | |||
| Maximum Pulsed Current IWB, IWA | IWB, IWA | -20 | 20 | mA | Pulsed | 5 | |
| Maximum Continuous Current IWB | IWB | -1 | 1 | mA | RWB ≤ 5 kΩ, A open | 5 | |
| Maximum Continuous Current IWA | IWA | -1 | 1 | mA | RWA ≤ 5 kΩ, B open | 5 | |
| Maximum Continuous Current IAB | IAB | -500 | 500 | μA | RAB = 10 kΩ | 5 | |
| Operating Temperature Range | TA | -40 | 105 | °C | 5 | ||
| Maximum Junction Temperature | TJmax | 150 | °C | 5 | |||
| Storage Temperature | TSTG | -65 | 150 | °C | 5 | ||
| Lead Temperature (Soldering) | TLEAD | 245 | °C | 10 s, 30 s | 5 | ||
| End-to-End Resistance | RAB | 10 | kΩ | 1 | |||
| Resistance Temperature Coefficient | (ΔRAB/RAB)/ΔT × 106 | 35 | ppm/°C | 3 | |||
| Voltage Divider Temperature Coefficient | (ΔVW/VW)/ΔT × 106 | 5 | ppm/°C | Midscale | 3 | ||
| Thermal Resistance Junction-to-Ambient | θJA | 230 | °C/W | Package power dissipation = (TJmax, TA) / θJA | 5 |
CAD (KiCad official)
- Symbol:
AD5227BUJZ10-RL7 - Footprint:
Package_TO_SOT_SMD:TSOT-23-8 - 3D model: TSOT-23-8 (KiCad packages3D, STEP)
- 3D model files:
ad5227bujz10-rl7-etched.step/ad5227bujz10-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5227bujz10-rl7.step/ad5227bujz10-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (16 pp, sha256
1418a20c179959d7, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).