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TF2106-3AS
Public Made by Adomby adom
TFSS Gate Drivers, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTF2106-3AS
TFSS · Gate Drivers · PDIP-8
TF2106-3AS from TFSS, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low-side and logic fixed supply, recommended operating range 10V to 20V (absolute maximum 24V). |
| 2 | HIN | input | Logic input for high-side gate driver output (HO), in phase; TTL/CMOS compatible down to 3.3V with Schmitt trigger and internal pull-down. |
| 3 | LIN | input | Logic input for low-side gate driver output (LO), in phase; TTL/CMOS compatible down to 3.3V with Schmitt trigger and internal pull-down. |
| 4 | COM | power_in | Low-side return, common ground for the low-side gate driver and logic. |
| 5 | LO | output | Low-side gate drive output, swings from COM to VCC. |
| 6 | VS | power_in | High-side floating supply return, operating offset up to 600V (absolute maximum VB-24V to VB+0.3V). |
| 7 | HO | output | High-side gate drive output, swings from VS to VB. |
| 8 | VB | power_in | High-side floating supply, VS+10V to VS+20V in operation (absolute maximum 624V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TFSS |
| Package | PDIP-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic 1 input voltage | VIH | 2.5 | V | VCC = 10V to 20V | 4 | ||
| Logic 0 input voltage | VIL | 0.6 | V | VCC = 10V to 20V | 4 | ||
| High level output voltage, VBIAS - VO | VOH | 0.05 | 0.2 | V | IO = 2mA | 4 | |
| Low level output voltage | VOL | 0.02 | 0.1 | V | IO = 2mA | 4 | |
| Offset supply leakage current | ILK | 50 | mA | VB = VS = 600V | 4 | ||
| Quiescent VBS supply current | IBSQ | 20 | 75 | 130 | mA | VIN = 0V or 5V | 4 |
| Quiescent VCC supply current | ICCQ | 60 | 120 | 180 | mA | VIN = 0V or 5V | 4 |
| Logic 1 input bias current | IIN+ | 5 | 20 | mA | VIN = 5V | 4 | |
| Logic 0 input bias current | IIN- | 2 | mA | VIN = 0V | 4 | ||
| VCC supply under-voltage positive going threshold | VCCUV+ | 8 | 8.9 | 9.8 | V | 4 | |
| VCC supply under-voltage negative going threshold | VCCUV- | 7.4 | 8.2 | 9 | V | 4 | |
| VBS supply under-voltage positive going threshold | VBSUV+ | 8 | 8.9 | 9.8 | V | 4 | |
| VBS supply under-voltage negative going threshold | VBSUV- | 7.4 | 8.2 | 9 | V | 4 | |
| Undervoltage lockout hysteresis | VUVLOH | 0.3 | 0.7 | V | 4 | ||
| Output high short circuit pulsed current | IO+ | 130 | 290 | mA | VO = 0V, VIN = Logic "1", PW ≤ 10 ms | 4 | |
| Output low short circuit pulsed current | IO- | 270 | 600 | mA | VO = 15V, VIN = Logic "0", PW ≤ 10 ms | 4 | |
| Turn-on propagation delay | tON | 220 | 300 | ns | VS = 0V | 4 | |
| Turn-off propagation delay | tOFF | 200 | 280 | ns | VS = 0V or 600V | 4 | |
| Turn-on rise time | tr | 100 | 220 | ns | 4 | ||
| Turn-off fall time | tf | 35 | 80 | ns | VS = 0V | 4 | |
| Delay matching | tDM | 30 | ns | 4 | |||
| High side floating supply voltage | VB | -0.3 | 624 | V | 3 | ||
| High side floating supply offset voltage | VS | -24 | 0.3 | V | VB-24V to VB+0.3V (relative to VB) | 3 | |
| High side floating output voltage | VHO | -0.3 | 0.3 | V | VS-0.3V to VB+0.3V (relative to VS and VB) | 3 | |
| Offset supply voltage transient | dVS/dt | 50 | V/ns | 3 | |||
| Low side and logic fixed supply voltage | VCC | -0.3 | 24 | V | 3 | ||
| Low side output voltage | VLO | -0.3 | 0.3 | V | -0.3V to VCC+0.3V (relative to VCC) | 3 | |
| Logic input voltage (HIN and LIN) | VIN | -0.3 | 0.3 | V | -0.3V to VCC+0.3V (relative to VCC) | 3 | |
| Package power dissipation PDIP-8 | PD | 1 | W | TA ≤ 25 °C | 3 | ||
| Junction operating temperature | TJ | 150 | °C | 3 | |||
| Lead temperature | TL | 300 | °C | soldering, 10s | 3 | ||
| Storage temperature range | Tstg | -55 | 150 | °C | 3 | ||
| High side floating supply absolute voltage | VB | 10 | 20 | V | VS + 10 to VS + 20 (relative to VS) | 3 | |
| High side floating supply offset voltage | VS | 600 | V | NOTE3: logic operational for VS = -5 to +600V | 3 | ||
| Low side and logic fixed supply voltage | VCC | 10 | 20 | V | 3 | ||
| Low side output voltage | VLO | 0 | 20 | V | 0 to VCC (max given as VCC) | 3 | |
| Logic input voltage (HIN and LIN) | VIN | 0 | 5 | V | 3 | ||
| Ambient temperature | TA | -40 | 125 | °C | 3 | ||
| PDIP-8 thermal resistance junction-to-case | θJC | 35 | °C/W | Mounted on standard JEDEC 2-layer FR-4 board | 3 | ||
| PDIP-8 thermal resistance junction-to-ambient | θJA | 125 | °C/W | Mounted on standard JEDEC 2-layer FR-4 board | 3 |
CAD (KiCad official)
- Symbol:
TF2106-3AS - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files:
tf2106-3as-etched.step/tf2106-3as-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tf2106-3as.step/tf2106-3as.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TFSS datasheet (16 pp, sha256
dabb2ac44be81054, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).