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AD5696BCPZ-RL7
Public Made by Adomby adom
Analog Devices Pre-ordered Chips, LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5696BCPZ-RL7
Analog Devices · Pre-ordered Chips · LFCSP-16(3x3)
AD5696BCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A with a rail-to-rail output amplifier. |
| 2 | GND | power_in | Ground reference point for all circuitry on the part. |
| 3 | VDD | power_in | Power supply input operable from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 4 | VOUTC | output | Analog output voltage from DAC C with a rail-to-rail output amplifier. |
| 5 | VOUTD | output | Analog output voltage from DAC D with a rail-to-rail output amplifier. |
| 6 | SDA | bidirectional | Open-drain serial data line, used with SCL to clock data into or out of the 24-bit input shift register, and to be pulled to the supply with an external pull-up resistor. |
| 7 | LDAC | input | Load DAC pin in asynchronous or synchronous update mode; pulsing it low updates any or all DAC registers with new input data, and it can be tied permanently low. |
| 8 | GAIN | input | Gain select pin; tied to GND sets all four DAC spans to 0 V to VREF, and tied to VLOGIC sets all four spans to 0 V to 2 × VREF. |
| 9 | VLOGIC | power_in | Digital power supply with a voltage range of 1.62 V to 5.5 V. |
| 10 | A0 | input | Address input that sets the first LSB of the 7-bit slave address. |
| 11 | SCL | input | Serial clock line used with SDA to clock data into or out of the 24-bit input shift register. |
| 12 | A1 | input | Address input that sets the second LSB of the 7-bit slave address. |
| 13 | RESET | input | Asynchronous reset input that is falling-edge sensitive; when low it loads zero scale or midscale (per RSTSEL) into the input and DAC registers and causes all LDAC pulses to be ignored. |
| 14 | RSTSEL | input | Power-on reset select pin; tied to GND powers all four DACs up to zero scale, and tied to VLOGIC powers all four DACs up to midscale. |
| 15 | VREF | power_in | Reference input voltage for the DACs. |
| 16 | VOUTB | output | Analog output voltage from DAC B with a rail-to-rail output amplifier. |
| 17 | EPAD | passive | Exposed pad on the LFCSP package that must be tied to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | Interface ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL) | -2 | 1 | 2 | LSB | Gain = 2 | 4 | |
| Relative Accuracy (INL) | -3 | 1 | 3 | LSB | Gain = 1 | 4 | |
| Differential Nonlinearity | -1 | 1 | LSB | Guaranteed monotonic by design | 4 | ||
| Offset Error | -1.5 | 0.1 | 1.5 | mV | 4 | ||
| Full-Scale Error | -0.1 | 0.01 | 0.1 | % of FSR | All 1s loaded to DAC register | 4 | |
| Gain Error | -0.1 | 0.02 | 0.1 | % of FSR | 4 | ||
| Total Unadjusted Error | -0.1 | 0.01 | 0.1 | % of FSR | Gain = 2 | 4 | |
| Total Unadjusted Error | -0.2 | 0.2 | % of FSR | Gain = 1 | 4 | ||
| Offset Error Drift | -1 | 1 | µV/°C | 4 | |||
| Gain Temperature Coefficient | -1 | 1 | ppm Of FSR/°C | 4 | |||
| DC Power Supply Rejection Ratio | 0.15 | mV/V | DAC code = midscale; VDD = 5 V ± 10% | 4 | |||
| DC Crosstalk due to single channel full-scale output change | -2 | 2 | µV | Due to single channel, full-scale output change | 4 | ||
| DC Crosstalk due to load current change | -3 | 3 | µV/mA | Due to load current change | 4 | ||
| DC Crosstalk due to power-down | -2 | 2 | µV | Due to power-down (per channel) | 4 | ||
| Capacitive Load Stability | 2 | nF | RL = ∞ | 4 | |||
| Capacitive Load Stability | 10 | nF | RL = 1 kΩ | 4 | |||
| Resistive Load | 1 | kΩ | 4 | ||||
| Load Regulation | 80 | µV/mA | DAC code = midscale; 5 V ± 10%; −30 mA ≤ IOUT ≤ +30 mA | 4 | |||
| Short-Circuit Current | 40 | mA | VDD = 5 V | 4 | |||
| Load Impedance at Rails | 25 | Ω | See Figure 20 | 4 | |||
| Power-Up Time | 2.5 | µs | Coming out of power-down mode; VDD = 5 V | 4 | |||
| Reference Current | 90 | µA | VREF = VDD = 5.5 V, gain = 1 | 4 | |||
| Reference Current | 180 | µA | VREF = VDD = 5.5 V, gain = 2 | 4 | |||
| Reference Input Impedance | 16 | kΩ | Gain = 2 | 4 | |||
| Reference Input Impedance | 32 | kΩ | Gain = 1 | 4 | |||
| Reference Input Range | 1 | V | Gain = 1 | 4 | |||
| Input Current | -2 | 2 | µA | Per pin | 4 | ||
| Pin Capacitance | 2 | pF | 4 | ||||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 3 mA | 4 | ||
| Floating State Output Capacitance | 4 | pF | 4 | ||||
| VLOGIC Supply Voltage | VLOGIC | 1.62 | 5.5 | V | 4 | ||
| Logic Supply Current | ILOGIC | 3 | µA | 4 | |||
| VDD Supply Voltage | VDD | 2.7 | 5.5 | V | Gain = 1 | 4 | |
| Normal Mode Supply Current | IDD | 0.59 | 0.7 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V | 4 | |
| All Power-Down Modes Supply Current | IDD | 1 | 4 | µA | −40°C to +85°C | 4 | |
| All Power-Down Modes Supply Current | IDD | 6 | µA | −40°C to +105°C | 4 | ||
| Output Voltage Settling Time | 5 | 8 | µs | AD5696; ¼ to ¾ scale settling to ±2 LSB | 5 | ||
| Slew Rate | 0.8 | V/µs | 5 | ||||
| Digital-to-Analog Glitch Impulse | 0.5 | nV × sec | 1 LSB change around major carry transition | 5 | |||
| Digital Feedthrough | 0.13 | nV × sec | 5 | ||||
| Multiplying Bandwidth | 500 | kHz | 5 | ||||
| Digital Crosstalk | 0.1 | nV × sec | 5 | ||||
| Analog Crosstalk | 0.2 | nV × sec | 5 | ||||
| DAC-to-DAC Crosstalk | 0.3 | nV × sec | 5 | ||||
| Total Harmonic Distortion | -80 | dB | At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz | 5 | |||
| Output Noise Spectral Density | 100 | nV/√Hz | DAC code = midscale, 10 kHz, gain = 2 | 6 | |||
| Output Noise | 6 | µV p-p | 0.1 Hz to 10 Hz | 6 | |||
| Signal-to-Noise Ratio | SNR | 90 | dB | At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz | 6 | ||
| Spurious-Free Dynamic Range | SFDR | 83 | dB | At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz | 6 | ||
| Signal-to-Noise-and-Distortion Ratio | SINAD | 80 | dB | At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz | 6 |
CAD (KiCad official)
- Symbol:
AD5696BCPZ-RL7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
ad5696bcpz-rl7-etched.step/ad5696bcpz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5696bcpz-rl7.step/ad5696bcpz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
6511b9dc603ebc4c, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).