component
TPS5430QDDARQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS5430QDDARQ1
Texas Instruments · DC-DC Converters · SOP-8-EP
TPS5430QDDARQ1 from Texas Instruments, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | output | Boost capacitor for the high-side FET gate driver; connect a 0.01µF low ESR capacitor rated for at least 10V from BOOT to PH. |
| 2 | NC | unconnected | No connect, not internally connected. |
| 3 | NC | unconnected | No connect, not internally connected. |
| 4 | VSENSE | input | Feedback voltage for the regulator; connect to the output voltage divider. |
| 5 | ENA | input | On and off control: below 0.5V the device stops switching and above 1.3V it starts switching; it has an internal 1.5MΩ pullup, so do not connect it to ground through a resistor. |
| 6 | GND | power_in | Ground; connect to DAP, which must be connected to the exposed pad for proper operation. |
| 7 | VIN | power_in | Input supply voltage; bypass to GND with a high quality low ESR ceramic capacitor placed within 1mm of the VIN pin and within 1mm of the GND pin. |
| 8 | PH | output | Source of the high side power MOSFET, connected to the external inductor and diode. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VIN to GND | VIN | -0.3 | 40 | V | 4 | ||
| Input voltage ENA to GND | -0.3 | 7 | V | 4 | |||
| Input voltage VSENSE to GND | -0.3 | 3 | V | 4 | |||
| Output voltage BOOT to PH | -0.3 | 6 | V | 4 | |||
| Output voltage BOOT to GND | -0.3 | V | 4 | ||||
| Output voltage PH to GND, steady-state | -0.6 | 40 | V | Steady-state | 4 | ||
| Output voltage PH to GND, transient | -1.2 | V | transient < 10ns | 4 | |||
| Source current PH leakage current | 10 | µA | 4 | ||||
| TJ Operating virtual junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Tstg Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD Human body model (HBM) | V(ESD) | -2000 | 2000 | V | Per AEC Q100-002, ESD classification level 2 | 4 | |
| ESD Charged device model (CDM) | V(ESD) | -750 | 750 | V | Per AEC Q100-011, ESD classification level C5 | 4 | |
| Input voltage range | VIN | 5.5 | 36 | V | 4 | ||
| TJ Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| VIN quiescent current | IQ(VIN) | 2 | 4.4 | mA | Non-switching, VSENSE = 2V, PH pin open | 5 | |
| VIN shutdown supply current | ISD(VIN) | 15 | 50 | µA | Shutdown, ENA = 0V | 5 | |
| VIN UVLO rising threshold | VINUVLO(R) | 5.3 | 5.5 | V | VVIN rising | 5 | |
| FB voltage | VFB | 1.202 | 1.221 | 1.239 | V | TJ = 25°C | 5 |
| FB voltage | VFB | 1.196 | 1.221 | 1.245 | V | TJ = -40°C to 125°C | 5 |
| Switching frequency | fSW | 400 | 500 | 600 | kHz | 5 | |
| Internal slow-start time (0 to 100%) | tSS | 5.4 | 8 | 10 | ms | 5 | |
| High-side peak current limit | IHS(OC) | 4 | 5 | 7 | A | 5 | |
| Hiccup time before re-start | 13 | 16 | 21 | ms | 5 | ||
| High-side MOSFET on-resistance | RDSON(HS) | 100 | 230 | mΩ | VIN = 12V, VBOOT-SW = 4.5V | 5 | |
| Thermal shutdown threshold | TJ(SD) | 135 | 162 | °C | Temperature rising | 5 | |
| Minimum ON pulse width | tON(min) | 150 | 200 | ns | 5 | ||
| Maximum duty cycle | DMAX | 87 | 89 | % | fSW = 500kHz | 5 | |
| ENA voltage rising threshold | VEN(R) | 1.3 | V | 5 | |||
| ENA voltage falling threshold | VEN(F) | 0.5 | V | 5 | |||
| ENA voltage hysteresis | VEN(H) | 325 | mV | 5 | |||
| VIN UVLO hysteresis | VINUVLO(H) | 0.35 | V | 5 | |||
| High-side MOSFET on-resistance | RDSON(HS) | 125 | mΩ | VIN = 5.5V, VBOOT-SW = 4.0V | 5 | ||
| Thermal shutdown hysteresis | TJ(HYS) | 14 | °C | 5 | |||
| Junction-to-ambient thermal resistance (TPS5430EVM) | RθJA | 45 | °C/W | 4 | |||
| Junction-to-ambient thermal resistance (JESD 51-7) | RθJA | 42.3 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 46 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 15 | °C/W | 4 | |||
| Junction-to-top characterization parameter | ψJT | 5.2 | °C/W | 4 | |||
| Junction-to-board characterization parameter | ψJB | 15.3 | °C/W | 4 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 6 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS5430QDDARQ1 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
tps5430qddarq1-etched.step/tps5430qddarq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps5430qddarq1.step/tps5430qddarq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
b87725776c87a4a8, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).