component

74HCT244PW

Public Unreviewed

by Ray

Nexperia Buffer/Driver/Transceiver, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentlogic74hct244pw
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Datasheet

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF
Contents

README

markdown

74HCT244PW

Nexperia · Buffer/Driver/Transceiver · TSSOP-20

74HCT244PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable input for bank 1 (active LOW). A LOW enables the 1Y0-1Y3 outputs; a HIGH forces them to the high-impedance OFF-state.
2 1A0 input Data input for bank 1, channel 0. Buffered non-inverting path to 1Y0 when 1OE is LOW.
3 2Y0 tri_state Bus output for bank 2, channel 0. Non-inverting buffered output of 2A0; high-impedance when 2OE is HIGH.
4 1A1 input Data input for bank 1, channel 1. Buffered non-inverting path to 1Y1 when 1OE is LOW.
5 2Y1 tri_state Bus output for bank 2, channel 1. Non-inverting buffered output of 2A1; high-impedance when 2OE is HIGH.
6 1A2 input Data input for bank 1, channel 2. Buffered non-inverting path to 1Y2 when 1OE is LOW.
7 2Y2 tri_state Bus output for bank 2, channel 2. Non-inverting buffered output of 2A2; high-impedance when 2OE is HIGH.
8 1A3 input Data input for bank 1, channel 3. Buffered non-inverting path to 1Y3 when 1OE is LOW.
9 2Y3 tri_state Bus output for bank 2, channel 3. Non-inverting buffered output of 2A3; high-impedance when 2OE is HIGH.
10 GND power_in Ground reference (0 V).
11 2A3 input Data input for bank 2, channel 3. Buffered non-inverting path to 2Y3 when 2OE is LOW.
12 1Y3 tri_state Bus output for bank 1, channel 3. Non-inverting buffered output of 1A3; high-impedance when 1OE is HIGH.
13 2A2 input Data input for bank 2, channel 2. Buffered non-inverting path to 2Y2 when 2OE is LOW.
14 1Y2 tri_state Bus output for bank 1, channel 2. Non-inverting buffered output of 1A2; high-impedance when 1OE is HIGH.
15 2A1 input Data input for bank 2, channel 1. Buffered non-inverting path to 2Y1 when 2OE is LOW.
16 1Y1 tri_state Bus output for bank 1, channel 1. Non-inverting buffered output of 1A1; high-impedance when 1OE is HIGH.
17 2A0 input Data input for bank 2, channel 0. Buffered non-inverting path to 2Y0 when 2OE is LOW.
18 1Y0 tri_state Bus output for bank 1, channel 0. Non-inverting buffered output of 1A0; high-impedance when 1OE is HIGH.
19 2OE input Output enable input for bank 2 (active LOW). A LOW enables the 2Y0-2Y3 outputs; a HIGH forces them to the high-impedance OFF-state.
20 VCC power_in Positive supply voltage. 74HCT244: 4.5 V to 5.5 V recommended (absolute max 7 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • 74HCT244PW
  • 74HCT244PWD
  • 74HCT244PWBQ

CAD (KiCad official)

  • Symbol: 74HCT244PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 7d5786046ad334eb, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF