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SN74LS375N
Public Made by Adomby adom
Texas Instruments Latches, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LS375N
Texas Instruments · Latches · PDIP-16
SN74LS375N from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1D | input | Data input of latch 1, transferred to 1Q when 1C,2C is high; high level at least 2 V, low level at most 0.8 V. |
| 2 | 1Q̅ | output | Complementary output of latch 1, sources up to 0.4 mA high and sinks 8 mA low. |
| 3 | 1Q | output | True output of latch 1, follows 1D while 1C,2C is high and holds when low; IOH -0.4 mA, IOL 8 mA max. |
| 4 | 1C,2C | input | Shared enable input for latches 1 and 2; transparent when high, latched when low. |
| 5 | 2Q | output | True output of latch 2, follows 2D while 1C,2C is high; IOH -0.4 mA, IOL 8 mA max. |
| 6 | 2Q̅ | output | Complementary output of latch 2, IOH -0.4 mA, IOL 8 mA max. |
| 7 | 2D | input | Data input of latch 2, transferred to 2Q when 1C,2C is high; VIH 2 V min, VIL 0.8 V max. |
| 8 | GND | power_in | Ground supply terminal, reference for all voltages. |
| 9 | 3D | input | Data input of latch 3, transferred to 3Q when 3C,4C is high; VIH 2 V min, VIL 0.8 V max. |
| 10 | 3Q̅ | output | Complementary output of latch 3, IOH -0.4 mA, IOL 8 mA max. |
| 11 | 3Q | output | True output of latch 3, follows 3D while 3C,4C is high; IOH -0.4 mA, IOL 8 mA max. |
| 12 | 3C,4C | input | Shared enable input for latches 3 and 4; transparent when high, latched when low. |
| 13 | 4Q | output | True output of latch 4, follows 4D while 3C,4C is high; IOH -0.4 mA, IOL 8 mA max. |
| 14 | 4Q̅ | output | Complementary output of latch 4, IOH -0.4 mA, IOL 8 mA max. |
| 15 | 4D | input | Data input of latch 4, transferred to 4Q when 3C,4C is high; VIH 2 V min, VIL 0.8 V max. |
| 16 | VCC | power_in | Supply voltage, 4.75 V to 5.25 V recommended for SN74LS375, 7 V absolute maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-16 |
| Category | Logic ICs |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74LS375N - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74ls375n-etched.step/sn74ls375n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls375n.step/sn74ls375n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (10 pp, sha256
337f70032795b839, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).