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CD4093BQM96G4Q1
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4093BQM96G4Q1
Texas Instruments · Logic Gates · SOIC-14
CD4093BQM96G4Q1 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of NAND gate 1 with Schmitt-trigger action; maximum input current is 1 µA at 18 V over the full package temperature range. |
| 2 | B | input | Input B of NAND gate 1 (J = A • B) with Schmitt-trigger action; maximum input current is 1 µA at 18 V over the full package temperature range. |
| 3 | J | output | Output of NAND gate 1, J = A • B, with standardized, symmetrical output characteristics. |
| 4 | K | output | Output of NAND gate 2, K = C • D, with standardized, symmetrical output characteristics. |
| 5 | C | input | Input C of NAND gate 2 with Schmitt-trigger action; maximum input current is 1 µA at 18 V over the full package temperature range. |
| 6 | D | input | Input D of NAND gate 2 (K = C • D) with Schmitt-trigger action; maximum input current is 1 µA at 18 V over the full package temperature range. |
| 7 | VSS | power_in | Negative supply terminal (VSS), the reference for the device supply range of 3 V to 18 V. |
| 8 | E | input | Input E of NAND gate 4 (L = E • F) with Schmitt-trigger action; maximum input current is 1 µA at 18 V over the full package temperature range. |
| 9 | F | input | Input F of NAND gate 4 (L = E • F) with Schmitt-trigger action; maximum input current is 1 µA at 18 V over the full package temperature range. |
| 10 | L | output | Output of NAND gate 4, L = E • F, with standardized, symmetrical output characteristics. |
| 11 | M | output | Output of NAND gate 3, M = G • H, with standardized, symmetrical output characteristics. |
| 12 | G | input | Input G of NAND gate 3 (M = G • H) with Schmitt-trigger action; maximum input current is 1 µA at 18 V over the full package temperature range. |
| 13 | H | input | Input H of NAND gate 3 (M = G • H) with Schmitt-trigger action; maximum input current is 1 µA at 18 V over the full package temperature range. |
| 14 | VDD | power_in | Positive supply terminal (VDD); recommended supply voltage range is 3 V to 18 V relative to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | 3 | 18 | V | TA = full package temperature range | 6 | |
| DC supply voltage range | VDD | -0.5 | 20 | V | 6 | ||
| Input voltage range, all inputs | VI | -0.5 | V | 6 | |||
| DC input current, any one input | -10 | 10 | mA | 6 | |||
| Device dissipation per output transistor | 100 | mW | TA, all package types | 6 | |||
| Operating temperature range | TA | -40 | 125 | °C | 6 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 6 | ||
| Quiescent device current, 25°C | IDD | 0.02 | 1 | µA | VDD = 5 V; TA = 25°C | 7 | |
| Quiescent device current, 125°C | IDD | 30 | µA | VDD = 5 V; TA = 125°C | 7 | ||
| Quiescent device current, 25°C | IDD | 0.02 | 2 | µA | VDD = 10 V; TA = 25°C | 7 | |
| Quiescent device current, 125°C | IDD | 60 | µA | VDD = 10 V; TA = 125°C | 7 | ||
| Quiescent device current, 25°C | IDD | 0.02 | 4 | µA | VDD = 15 V; TA = 25°C | 7 | |
| Quiescent device current, 125°C | IDD | 120 | µA | VDD = 15 V; TA = 125°C | 7 | ||
| Quiescent device current, 25°C | IDD | 0.04 | 20 | µA | VDD = 20 V; TA = 25°C | 7 | |
| Quiescent device current, 125°C | IDD | 600 | µA | VDD = 20 V; TA = 125°C | 7 | ||
| Positive trigger threshold voltage, config A | VP | 2.2 | 2.9 | V | VDD = 5 V; Note A (inputs 1,5,8,12 or 2,6,9,13) | 7 | |
| Positive trigger threshold voltage, config A | VP | 4.6 | 5.9 | V | VDD = 10 V; Note A | 7 | |
| Positive trigger threshold voltage, config A | VP | 6.8 | 8.8 | V | VDD = 15 V; Note A | 7 | |
| Positive trigger threshold voltage, config B | VP | 2.6 | 3.3 | V | VDD = 5 V; Note B (inputs 1,2; 5,6; 8,9; or 12,13) | 7 | |
| Positive trigger threshold voltage, config B | VP | 5.6 | 7 | V | VDD = 10 V; Note B | 7 | |
| Positive trigger threshold voltage, config B | VP | 6.3 | 9.4 | V | VDD = 15 V; Note B | 7 | |
| Positive trigger threshold voltage, config A | VP | 2.9 | 3.6 | V | VDD = 5 V; Note A | 7 | |
| Positive trigger threshold voltage, config A | VP | 5.9 | 7.1 | V | VDD = 10 V; Note A | 7 | |
| Positive trigger threshold voltage, config A | VP | 8.8 | 10.8 | V | VDD = 15 V; Note A | 7 | |
| Positive trigger threshold voltage, config B | VP | 3.3 | 4 | V | VDD = 5 V; Note B | 7 | |
| Positive trigger threshold voltage, config B | VP | 7 | 8.2 | V | VDD = 10 V; Note B | 7 | |
| Positive trigger threshold voltage, config B | VP | 9.4 | 12.7 | V | VDD = 15 V; Note B | 7 | |
| Negative trigger threshold voltage, config A | VN | 0.9 | 1.9 | V | VDD = 5 V; Note A | 7 | |
| Negative trigger threshold voltage, config A | VN | 2.5 | 3.9 | V | VDD = 10 V; Note A | 7 | |
| Negative trigger threshold voltage, config A | VN | 4 | 5.8 | V | VDD = 15 V; Note A | 7 | |
| Negative trigger threshold voltage, config B | VN | 1.4 | 2.3 | V | VDD = 5 V; Note B | 7 | |
| Negative trigger threshold voltage, config B | VN | 3.4 | 5.1 | V | VDD = 10 V; Note B | 7 | |
| Negative trigger threshold voltage, config B | VN | 4.8 | 7.3 | V | VDD = 15 V; Note B | 7 | |
| Negative trigger threshold voltage, config A | VN | 1.9 | 2.8 | V | VDD = 5 V; Note A | 7 | |
| Negative trigger threshold voltage, config A | VN | 3.9 | 5.2 | V | VDD = 10 V; Note A | 7 | |
| Negative trigger threshold voltage, config A | VN | 5.8 | 7.4 | V | VDD = 15 V; Note A | 7 | |
| Negative trigger threshold voltage, config B | VN | 2.3 | 3.2 | V | VDD = 5 V; Note B | 7 | |
| Negative trigger threshold voltage, config B | VN | 5.1 | 6.6 | V | VDD = 10 V; Note B | 7 | |
| Negative trigger threshold voltage, config B | VN | 7.3 | 9.6 | V | VDD = 15 V; Note B | 7 | |
| Output voltage low level | VOL | 0 | 0.05 | V | VDD = 5 V | 8 | |
| Output voltage high level | VOH | 4.95 | 5 | V | VDD = 5 V | 8 | |
| Output voltage high level | VOH | 9.95 | 10 | V | VDD = 10 V | 8 | |
| Output voltage high level | VOH | 14.95 | V | VDD = 15 V | 8 | ||
| Output low (sink) current, 25°C | IOL | 0.51 | 1 | mA | VO = 0.4 V; VI = 0,5 V; VDD = 5 V | 8 | |
| Output low (sink) current, 25°C | IOL | 1.3 | 2.6 | mA | VO = 0.5 V; VI = 0,10 V; VDD = 10 V | 8 | |
| Output low (sink) current, 25°C | IOL | 3.4 | 6.8 | mA | VO = 1.5 V; VI = 0,15 V; VDD = 15 V | 8 | |
| Output high (source) current, 25°C | IOH | -0.51 | -1 | mA | VO = 4.6 V; VI = 0,5 V; VDD = 5 V | 8 | |
| Output high (source) current, 25°C | IOH | -1.6 | -3.2 | mA | VO = 2.5 V; VI = 0,5 V; VDD = 5 V | 8 | |
| Output high (source) current, 25°C | IOH | -1.3 | -2.6 | mA | VO = 9.5 V; VI = 0,10 V; VDD = 10 V | 8 | |
| Output high (source) current, 25°C | IOH | -3.4 | -6.8 | mA | VO = 13.5 V; VI = 0,15 V; VDD = 15 V | 8 | |
| Propagation delay time, tPHL, tPLH | tPHL, tPLH | 190 | 380 | ns | VDD = 5 V; TA = 25°C, tr,tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 8 | |
| Propagation delay time, tPHL, tPLH | tPHL, tPLH | 90 | 180 | ns | VDD = 10 V; TA = 25°C, tr,tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 8 | |
| Propagation delay time, tPHL, tPLH | tPHL, tPLH | 65 | 130 | ns | VDD = 15 V; TA = 25°C, tr,tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 8 | |
| Transition time, tTHL, tTLH | tTHL, tTLH | 100 | 200 | ns | VDD = 5 V; TA = 25°C, tr,tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 8 | |
| Transition time, tTHL, tTLH | tTHL, tTLH | 50 | 100 | ns | VDD = 10 V; TA = 25°C, tr,tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 8 | |
| Transition time, tTHL, tTLH | tTHL, tTLH | 40 | 80 | ns | VDD = 15 V; TA = 25°C, tr,tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 8 | |
| Package thermal impedance | θJA | 86 | °C/W | JESD 51-7 (Note 1) | 6 |
CAD (KiCad official)
- Symbol:
CD4093BQM96G4Q1 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
cd4093bqm96g4q1-etched.step/cd4093bqm96g4q1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4093bqm96g4q1.step/cd4093bqm96g4q1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (14 pp, sha256
4d3149b0e2637d77, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).