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STM32F107RCT7
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F107RCT7
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32F107RCT7 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup supply of 1.8 to 3.6 V for the RTC, the 32 kHz oscillator and backup registers when VDD is not present. |
| 2 | PC13-TAMPER-RTC | bidirectional | General-purpose I/O PC13 (also TAMPER-RTC); it is supplied through the power switch, so in output mode it is limited to 2 MHz with a maximum load of 30 pF and only one such pin may be an output at a time. |
| 3 | PC14-OSC32_IN | bidirectional | General-purpose I/O PC14 or 32 kHz oscillator input (OSC32_IN); output use is limited to 2 MHz, maximum 30 pF, one pin at a time. |
| 4 | PC15-OSC32_OUT | bidirectional | General-purpose I/O PC15 or 32 kHz oscillator output (OSC32_OUT); output use is limited to 2 MHz, maximum 30 pF, one pin at a time. |
| 5 | OSC_IN | input | External 3 to 25 MHz crystal/oscillator input (HSE); on LQFP64 this pin is OSC_IN after reset. |
| 6 | OSC_OUT | output | External 3 to 25 MHz crystal oscillator output (HSE); on LQFP64 this pin is OSC_OUT after reset. |
| 7 | NRST | bidirectional | Device reset pin, listed as I/O in the pin definitions; no electrical limits for this pin are given in the pin table. |
| 8 | PC0 | bidirectional | General-purpose I/O PC0, not 5 V tolerant, with analog input ADC12_IN10. |
| 9 | PC1 | bidirectional | General-purpose I/O PC1, not 5 V tolerant, with analog input ADC12_IN11 and Ethernet MDC alternate function. |
| 10 | PC2 | bidirectional | General-purpose I/O PC2, not 5 V tolerant, with analog input ADC12_IN12 and ETH_MII_TXD2 alternate function. |
| 11 | PC3 | bidirectional | General-purpose I/O PC3, not 5 V tolerant, with analog input ADC12_IN13 and ETH_MII_TX_CLK alternate function. |
| 12 | VSSA | power_in | Analog ground, which must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply for the ADC, reset blocks, RCs and PLL, 2.0 to 3.6 V, with a minimum of 2.4 V when the ADC is used; it must be connected to VDD. |
| 14 | PA0-WKUP | bidirectional | General-purpose I/O PA0 with WKUP wakeup function, not 5 V tolerant, with ADC12_IN0, TIM2_CH1_ETR, TIM5_CH1 and USART2_CTS alternate functions. |
| 15 | PA1 | bidirectional | General-purpose I/O PA1, not 5 V tolerant, with USART2_RTS, ADC12_IN1, TIM5_CH2, TIM2_CH2 and Ethernet RX clock alternate functions. |
| 16 | PA2 | bidirectional | General-purpose I/O PA2, not 5 V tolerant, with USART2_TX, TIM5_CH3, ADC12_IN2, TIM2_CH3 and Ethernet MDIO alternate functions. |
| 17 | PA3 | bidirectional | General-purpose I/O PA3, not 5 V tolerant, with USART2_RX, TIM5_CH4, ADC12_IN3, TIM2_CH4 and ETH_MII_COL alternate functions. |
| 18 | VSS_4 | power_in | Digital ground pin, to be connected to the common VSS ground. |
| 19 | VDD_4 | power_in | Digital supply pin for I/Os and the internal regulator, 2.0 to 3.6 V. |
| 20 | PA4 | bidirectional | General-purpose I/O PA4, not 5 V tolerant, with SPI1_NSS, DAC_OUT1, USART2_CK, ADC12_IN4 and SPI3_NSS/I2S3_WS alternate functions. |
| 21 | PA5 | bidirectional | General-purpose I/O PA5, not 5 V tolerant, with SPI1_SCK, DAC_OUT2 and ADC12_IN5 alternate functions. |
| 22 | PA6 | bidirectional | General-purpose I/O PA6, not 5 V tolerant, with SPI1_MISO, ADC12_IN6, TIM3_CH1 and TIM1_BKIN alternate functions. |
| 23 | PA7 | bidirectional | General-purpose I/O PA7, not 5 V tolerant, with SPI1_MOSI, ADC12_IN7, TIM3_CH2, Ethernet RX_DV/CRS_DV and TIM1_CH1N alternate functions. |
| 24 | PC4 | bidirectional | General-purpose I/O PC4, not 5 V tolerant, with ADC12_IN14 and Ethernet RXD0 alternate functions. |
| 25 | PC5 | bidirectional | General-purpose I/O PC5, not 5 V tolerant, with ADC12_IN15 and Ethernet RXD1 alternate functions. |
| 26 | PB0 | bidirectional | General-purpose I/O PB0, not 5 V tolerant, with ADC12_IN8, TIM3_CH3, ETH_MII_RXD2 and TIM1_CH2N alternate functions. |
| 27 | PB1 | bidirectional | General-purpose I/O PB1, not 5 V tolerant, with ADC12_IN9, TIM3_CH4, ETH_MII_RXD3 and TIM1_CH3N alternate functions. |
| 28 | PB2 | bidirectional | 5 V tolerant general-purpose I/O PB2, which is also the BOOT1 boot-select pin. |
| 29 | PB10 | bidirectional | 5 V tolerant general-purpose I/O PB10 with I2C2_SCL, USART3_TX, ETH_MII_RX_ER and TIM2_CH3 alternate functions. |
| 30 | PB11 | bidirectional | 5 V tolerant general-purpose I/O PB11 with I2C2_SDA, USART3_RX, Ethernet TX_EN and TIM2_CH4 alternate functions. |
| 31 | VSS_1 | power_in | Digital ground pin, to be connected to the common VSS ground. |
| 32 | VDD_1 | power_in | Digital supply pin for I/Os and the internal regulator, 2.0 to 3.6 V. |
| 33 | PB12 | bidirectional | 5 V tolerant general-purpose I/O PB12 with SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX and Ethernet TXD0; SPI2/I2S2 and I2C2 are unavailable when Ethernet is used. |
| 34 | PB13 | bidirectional | 5 V tolerant general-purpose I/O PB13 with SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and Ethernet TXD1 alternate functions. |
| 35 | PB14 | bidirectional | 5 V tolerant general-purpose I/O PB14 with SPI2_MISO, TIM1_CH2N and USART3_RTS alternate functions. |
| 36 | PB15 | bidirectional | 5 V tolerant general-purpose I/O PB15 with SPI2_MOSI/I2S2_SD and TIM1_CH3N alternate functions. |
| 37 | PC6 | bidirectional | 5 V tolerant general-purpose I/O PC6 with I2S2_MCK and TIM3_CH1 alternate functions. |
| 38 | PC7 | bidirectional | 5 V tolerant general-purpose I/O PC7 with I2S3_MCK and TIM3_CH2 alternate functions. |
| 39 | PC8 | bidirectional | 5 V tolerant general-purpose I/O PC8 with TIM3_CH3 alternate function. |
| 40 | PC9 | bidirectional | 5 V tolerant general-purpose I/O PC9 with TIM3_CH4 alternate function. |
| 41 | PA8 | bidirectional | 5 V tolerant general-purpose I/O PA8 with USART1_CK, OTG_FS_SOF, TIM1_CH1 and MCO alternate functions. |
| 42 | PA9 | bidirectional | 5 V tolerant general-purpose I/O PA9 with USART1_TX, TIM1_CH2 and OTG_FS_VBUS alternate functions. |
| 43 | PA10 | bidirectional | 5 V tolerant general-purpose I/O PA10 with USART1_RX, TIM1_CH3 and OTG_FS_ID alternate functions. |
| 44 | PA11 | bidirectional | 5 V tolerant general-purpose I/O PA11 with USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM alternate functions. |
| 45 | PA12 | bidirectional | 5 V tolerant general-purpose I/O PA12 with USART1_RTS, OTG_FS_DP, CAN1_TX and TIM1_ETR alternate functions. |
| 46 | PA13 | bidirectional | 5 V tolerant pin whose default function is JTMS-SWDIO (serial wire debug data), with PA13 as the GPIO function. |
| 47 | VSS_2 | power_in | Digital ground pin, to be connected to the common VSS ground. |
| 48 | VDD_2 | power_in | Digital supply pin for I/Os and the internal regulator, 2.0 to 3.6 V. |
| 49 | PA14 | bidirectional | 5 V tolerant pin whose default function is JTCK-SWCLK (serial wire debug clock), with PA14 as the GPIO function. |
| 50 | PA15 | bidirectional | 5 V tolerant pin whose default function is JTDI, with SPI3_NSS/I2S3_WS, TIM2_CH1_ETR and SPI1_NSS alternate functions. |
| 51 | PC10 | bidirectional | 5 V tolerant general-purpose I/O PC10 with UART4_TX, USART3_TX and SPI3_SCK/I2S3_CK alternate functions. |
| 52 | PC11 | bidirectional | 5 V tolerant general-purpose I/O PC11 with UART4_RX, USART3_RX and SPI3_MISO alternate functions. |
| 53 | PC12 | bidirectional | 5 V tolerant general-purpose I/O PC12 with UART5_TX, USART3_CK and SPI3_MOSI/I2S3_SD alternate functions. |
| 54 | PD2 | bidirectional | 5 V tolerant general-purpose I/O PD2 with TIM3_ETR and UART5_RX alternate functions. |
| 55 | PB3 | bidirectional | 5 V tolerant pin whose default function is JTDO, with SPI3_SCK/I2S3_CK, TRACESWO, TIM2_CH2 and SPI1_SCK alternate functions. |
| 56 | PB4 | bidirectional | 5 V tolerant pin whose default function is NJTRST, with SPI3_MISO, TIM3_CH1 and SPI1_MISO alternate functions. |
| 57 | PB5 | bidirectional | General-purpose I/O PB5 (not 5 V tolerant per Table 5) with I2C1_SMBA, SPI3_MOSI, Ethernet PPS_OUT, I2S3_SD, TIM3_CH2, SPI1_MOSI and CAN2_RX alternate functions. |
| 58 | PB6 | bidirectional | 5 V tolerant general-purpose I/O PB6 with I2C1_SCL, TIM4_CH1, USART1_TX and CAN2_TX alternate functions. |
| 59 | PB7 | bidirectional | 5 V tolerant general-purpose I/O PB7 with I2C1_SDA, TIM4_CH2 and USART1_RX alternate functions. |
| 60 | BOOT0 | input | Boot pin sampled at startup to select boot from user Flash, system memory or embedded SRAM. |
| 61 | PB8 | bidirectional | 5 V tolerant general-purpose I/O PB8 with TIM4_CH3, Ethernet TXD3, I2C1_SCL and CAN1_RX alternate functions. |
| 62 | PB9 | bidirectional | 5 V tolerant general-purpose I/O PB9 with TIM4_CH4, I2C1_SDA and CAN1_TX alternate functions. |
| 63 | VSS_3 | power_in | Digital ground pin, to be connected to the common VSS ground. |
| 64 | VDD_3 | power_in | Digital supply pin for I/Os and the internal regulator, 2.0 to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32F107RCT7 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32f107rct7-etched.step/stm32f107rct7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f107rct7.step/stm32f107rct7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (108 pp, sha256
ca4bad652e5eb36d, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).