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CBM9001A-48AG

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Corebai Microelectronics USB Converters, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CBM9001A-48AG

Corebai Microelectronics · USB Converters · TQFP-48(7x7)

CBM9001A-48AG from Corebai Microelectronics, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connection; NC pins must be left unconnected.
2 NC unconnected No connection; NC pins must be left unconnected.
3 nWR input Active LOW write strobe input, used with nCS to write to registers and data memory.
4 nCS input Active LOW chip select input, used with nRD and nWR when accessing the device.
5 CM input Clock multiplier select: tie HIGH for a 12 MHz clock source and tie to ground for a 48 MHz clock source.
6 VDD1 power_in +3.3 VDC power for the USB transceivers; may be connected to VDD, with a recommended supply range of 3.0 V to 3.45 V.
7 DATA+ bidirectional USB differential data signal, HIGH side.
8 DATA- bidirectional USB differential data signal, LOW side.
9 GND power_in Ground connection for USB.
10 NC unconnected No connection; NC pins must be left unconnected.
11 NC unconnected No connection; NC pins must be left unconnected.
12 NC unconnected No connection; NC pins must be left unconnected.
13 NC unconnected No connection; NC pins must be left unconnected.
14 NC unconnected No connection; NC pins must be left unconnected.
15 VDD power_in +3.3 VDC device power; recommended supply range 3.0 V to 3.45 V.
16 CLK/X1 input Clock input or external crystal X1 connection; requires an external 12 or 48 MHz matching crystal or clock source.
17 X2 output External crystal X2 connection.
18 nRST input Device active-low reset input.
19 INTRQ output Active HIGH interrupt request output to the external controller.
20 GND power_in Device ground.
21 D0 bidirectional Data bit 0 of the microprocessor data/address bus.
22 NC unconnected No connection; NC pins must be left unconnected.
23 NC unconnected No connection; NC pins must be left unconnected.
24 NC unconnected No connection; NC pins must be left unconnected.
25 NC unconnected No connection; NC pins must be left unconnected.
26 NC unconnected No connection; NC pins must be left unconnected.
27 D1 bidirectional Data bit 1 of the microprocessor data/address bus.
28 D2 bidirectional Data bit 2 of the microprocessor data/address bus.
29 D3 bidirectional Data bit 3 of the microprocessor data/address bus.
30 GND power_in Device ground.
31 D4 bidirectional Data bit 4 of the microprocessor data/address bus.
32 D5 bidirectional Data bit 5 of the microprocessor data/address bus.
33 D6 bidirectional Data bit 6 of the microprocessor data/address bus.
34 NC unconnected No connection; NC pins must be left unconnected.
35 NC unconnected No connection; NC pins must be left unconnected.
36 NC unconnected No connection; NC pins must be left unconnected.
37 NC unconnected No connection; NC pins must be left unconnected.
38 NC unconnected No connection; NC pins must be left unconnected.
39 D7 bidirectional Data bit 7 of the microprocessor data/address bus.
40 M/S input Master/slave mode select: '1' selects slave and '0' selects master.
41 VDD power_in +3.3 VDC device power; recommended supply range 3.0 V to 3.45 V.
42 A0 input Address select: '0' selects the address pointer register and '1' selects a data buffer or register.
43 nDACK input Active LOW DMA acknowledge input for an external DMA controller; DMA is enabled only in slave mode, so this pin must be tied HIGH in host mode.
44 nDRQ output Active LOW DMA request output that forms the handshake with nDACK; leave unconnected in host mode.
45 nRD input Active LOW read strobe input, used with nCS to read registers and data memory.
46 NC unconnected No connection; NC pins must be left unconnected.
47 NC unconnected No connection; NC pins must be left unconnected.
48 NC unconnected No connection; NC pins must be left unconnected.

Key specifications

Parameter Value
Manufacturer Corebai Microelectronics
Package TQFP-48(7x7)
Category Interface
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature -40 125 °C 23
Voltage on any pin with respect to ground -0.3 6 V 23
Power Supply Voltage (VDD) VDD 4 V 23
Power Supply Voltage (VDD1) VDD1 4 V 23
Lead Temperature 180 °C 10 seconds 23
Power Supply Voltage VDD 3 3.3 3.45 V 23
Power Supply Voltage VDD1 3 3.45 V 23
Operating Temperature 0 65 °C 23
Input Voltage LOW VIL -0.3 0.8 V 24
Input Voltage HIGH (5 V Tolerant I/O) VIH 2 6 V 24
Output Voltage LOW VOL 0.4 V IOL = 4 mA 24
Output Voltage HIGH VOH 2.4 V IOH = -4 mA 24
Output Current HIGH IOH 4 mA 24
Output Current LOW IOL 4 mA 24
Input Leakage ILL -1 1 µA 24
Input Capacitance CIN 10 pF 24
Supply Current (VDD) including USB at FS ICC 21 25 mA Includes USB transceiver current at full speed (note 7) 24
Supply Current (VDD) Suspend w/ Clk & PLL Enabled ICCsus1 4.2 5 mA Suspend; 12 MHz clock input, internal PLL enabled (note 8) 24
Supply Current (VDD) Suspend no Clk & PLL Disabled ICCsus2 50 60 µA Suspend; external clock, PLL disabled (note 9) 24
Supply Current (VDD1) IUSB 10 mA 24
Transceiver Supply Current in Suspend IUSBSUS 10 µA 24
Differential Input Sensitivity (Data+, Data-) VIHYS 0.2 V Data+, Data- 24
USB Input Voltage HIGH VUSBIH 2 V Driven 24
USB Input Voltage LOW VUSBIL 0.8 V 24
USB Output Voltage HIGH VUSBOH 2 V 24
USB Output Voltage LOW VUSBOL 0 0.3 V 24
Output Impedance HIGH STATE ZUSBH 36 42 Ohms Includes external 24 Ohms ±1% resistor (note 11) 24
Output Impedance LOW STATE ZUSBL 36 42 Ohms Includes external 24 Ohms ±1% resistor (note 11) 24
Transceiver Supply p-p Current (3.3 V) IUSB 10 mA at FS 24
Write pulse width tWR 85 ns 25
Chip select set-up to nWR LOW tWCSU 0 ns 25
Chip select hold time tWSHLD 0 ns After nWR HIGH 25
A0 address setup time tWASU 85 ns 25
A0 address hold time tWAHLD 10 ns 25
Data to Write HIGH set-up time tWDSU 85 ns 25
Data hold time after Write HIGH tWDHLD 5 ns 25
nCS inactive to nCS asserted tCSCS 85 ns 25
nWR HIGH tWRHIGH 85 ns 25
Write Cycle Time for Auto Inc Mode Writes 170 ns Auto Inc Mode writes 25
nDACK low tdack 100 ns 28
nDACK to nRD low delay tddrdlo 0 ns 28
nDACK low to nDRQ high delay tdckdr 5 ns 28
nRD pulse width tdrdp 90 ns 28
Data hold after nDACK high tdhld 5 ns 28
Data access from nDACK low tddaccs 85 ns 28
nRD high to nDACK high tdrdack 0 ns 28
nDRQ low after nDACK high tdakrq 5 ns 28
DMA Read Cycle Time trdcycle 150 ns 28
nRST pulse width tRESET 16 clocks Clock 48 MHz nominal 28
nRST HIGH to nRD or nWR active tIOACT 16 clocks Clock 48 MHz nominal 28
Clock Period (48 MHz) tCLK 20 20.8 ns 29
Clock HIGH Time tHIGH 9 11 ns 29
Clock LOW Time tLOW 9 11 ns 29
Clock Rise Time tRISE 5 ns 29
Clock Fall Time tFALL 5 ns 29
Clock Duty Cycle 45 55 % 29
Clock Input Voltage at X1 (X2 Open) 1.5 V X2 open 23
Clock Frequency 48 MHz Note 6: 12 MHz clock source also supported 23

CAD (KiCad official)

  • Symbol: CBM9001A-48AG
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: cbm9001a-48ag-etched.step / cbm9001a-48ag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm9001a-48ag.step / cbm9001a-48ag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Corebai Microelectronics datasheet (29 pp, sha256 ce50f0aa730cf739, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF