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CDCVF2310PW

Public Made by Adom

by adom

Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CDCVF2310PW

Texas Instruments · Clock Buffers, Drivers, Distributors · TSSOP-24

CDCVF2310PW from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for the device.
2 VDD power_in DC power supply, 2.3 V to 3.6 V.
3 1Y0 output Buffered output clock 0 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins.
4 1Y1 output Buffered output clock 1 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins.
5 1Y2 output Buffered output clock 2 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins.
6 GND power_in Ground reference for the device.
7 GND power_in Ground reference for the device.
8 1Y3 output Buffered output clock 3 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins.
9 1Y4 output Buffered output clock 4 of bank 1; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins.
10 VDD power_in DC power supply, 2.3 V to 3.6 V.
11 1G input Active-high output enable for 1Y[0:4]; outputs follow CLK when held high and are low when held low (glitch-suppressed relative to CLK falling edge).
12 2Y4 output Buffered output clock 4 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins.
13 2G input Active-high output enable for 2Y[0:4]; outputs follow CLK when held high and are low when held low (glitch-suppressed relative to CLK falling edge).
14 VDD power_in DC power supply, 2.3 V to 3.6 V.
15 VDD power_in DC power supply, 2.3 V to 3.6 V.
16 2Y3 output Buffered output clock 3 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins.
17 2Y2 output Buffered output clock 2 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins.
18 GND power_in Ground reference for the device.
19 GND power_in Ground reference for the device.
20 2Y1 output Buffered output clock 1 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins.
21 2Y0 output Buffered output clock 0 of bank 2; 25-Ω on-chip series damping resistor; low after power-up regardless of control pins.
22 VDD power_in DC power supply, 2.3 V to 3.6 V.
23 VDD power_in DC power supply, 2.3 V to 3.6 V.
24 CLK input Input reference clock; the device operates up to 200 MHz at VDD = 3.3 V and up to 170 MHz at VDD = 2.3 V to 2.7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Clock/Timing
Pins 24

CAD (KiCad official)

  • Symbol: CDCVF2310PW
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: cdcvf2310pw-etched.step / cdcvf2310pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcvf2310pw.step / cdcvf2310pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 ca9739d492358f80, retrieved 2026-10-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF