component
AIP74LVC2G74YA8.TR
Public Made by Adomby adom
Wuxi I-core Elec Flip Flops, VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAIP74LVC2G74YA8.TR
Wuxi I-core Elec · Flip Flops · VSSOP-8
AIP74LVC2G74YA8.TR from Wuxi I-core Elec, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP | input | Clock input, edge-triggered on the LOW-to-HIGH transition. |
| 2 | D | input | Data input, must be stable one set-up time before the LOW-to-HIGH clock transition; accepts voltages up to 5.5V. |
| 3 | ~{Q} | output | Complement output of the flip-flop, with ±24mA drive at VCC=3.0V. |
| 4 | GND | power_in | Ground (0V) reference for all voltages. |
| 5 | Q | output | True output of the flip-flop, with ±24mA drive at VCC=3.0V and 5V tolerant. |
| 6 | R̅D̅ | input | Asynchronous reset-direct input, active LOW, operating independently of the clock. |
| 7 | S̅D̅ | input | Asynchronous set-direct input, active LOW, operating independently of the clock. |
| 8 | VCC | power_in | Supply voltage, recommended range 1.65V to 5.5V (absolute maximum 6.5V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I-core Elec |
| Package | VSSOP-8 |
| Category | Logic ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 6.5 | V | 5 | ||
| Input clamping current | IIK | -50 | mA | VI < 0V | 5 | ||
| Input voltage | VI | -0.5 | 6.5 | V | 5 | ||
| Output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0V | 5 | |
| Output voltage, active mode | VO | -0.5 | V | Active mode; max VCC+0.5 | 5 | ||
| Output voltage, power-down mode | VO | -0.5 | 6.5 | V | Power-down mode; VCC=0V | 5 | |
| Output current | IO | -50 | 50 | mA | VO=0V to VCC | 5 | |
| Supply current | ICC | 100 | mA | 5 | |||
| Ground current | IGND | -100 | mA | 5 | |||
| Total power dissipation | Ptot | 300 | mW | VSSOP8: above 110℃ derates linearly at 8mW/K | 5 | ||
| Storage temperature | Tstg | -65 | 150 | ℃ | 5 | ||
| Soldering temperature | TL | 250 | ℃ | 10s | 5 | ||
| Supply voltage | VCC | 1.65 | 5.5 | V | 5 | ||
| Input voltage | VI | 0 | 5.5 | V | 5 | ||
| Output voltage, active mode | VO | 0 | V | Active mode; max VCC | 5 | ||
| Output voltage, power-down mode | VO | 0 | 5.5 | V | Power-down mode; VCC=0V | 5 | |
| Ambient temperature | Tamb | -40 | 105 | ℃ | 5 | ||
| Input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC=1.65V to 2.7V | 5 | ||
| Input transition rise and fall rate | Δt/ΔV | 10 | ns/V | VCC=2.7V to 5.5V | 5 | ||
| HIGH-level input voltage | VIH | 1.7 | V | VCC=2.3V to 2.7V; Tamb=-40℃ to +105℃ | 7 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC=2.7V to 3.6V; Tamb=-40℃ to +105℃ | 7 | ||
| LOW-level input voltage | VIL | 0.7 | V | VCC=2.3V to 2.7V; Tamb=-40℃ to +105℃ | 7 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC=2.7V to 3.6V; Tamb=-40℃ to +105℃ | 7 | ||
| HIGH-level output voltage | VOH | 0.95 | V | VI = VIH or VIL; IO=-4mA; VCC=1.65V | 7 | ||
| HIGH-level output voltage | VOH | 1.7 | V | VI = VIH or VIL; IO=-8mA; VCC=2.3V | 7 | ||
| HIGH-level output voltage | VOH | 1.9 | V | VI = VIH or VIL; IO=-12mA; VCC=2.7V | 7 | ||
| HIGH-level output voltage | VOH | 2 | V | VI = VIH or VIL; IO=-24mA; VCC=3.0V | 7 | ||
| HIGH-level output voltage | VOH | 3.4 | V | VI = VIH or VIL; IO=-32mA; VCC=4.5V | 7 | ||
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; IO=100uA; VCC=1.65V to 5.5V | 7 | ||
| LOW-level output voltage | VOL | 0.7 | V | VI = VIH or VIL; IO=4mA; VCC=1.65V | 7 | ||
| LOW-level output voltage | VOL | 0.45 | V | VI = VIH or VIL; IO=8mA; VCC=2.3V | 7 | ||
| LOW-level output voltage | VOL | 0.6 | V | VI = VIH or VIL; IO=12mA; VCC=2.7V | 7 | ||
| LOW-level output voltage | VOL | 0.8 | V | VI = VIH or VIL; IO=24mA; VCC=3.0V | 7 | ||
| Input leakage current | II | -1 | 1 | uA | VI=5.5V or GND; VCC=0V to 5.5V | 7 | |
| Power-off leakage current | IOFF | -2 | 2 | uA | VI or VO=5.5V; VCC=0V | 7 | |
| Supply current | ICC | 4 | uA | VI=5.5V or GND; IO=0A; VCC=1.65V to 5.5V | 7 | ||
| Additional supply current | ΔICC | 500 | uA | per pin; VI=VCC-0.6V; IO=0A; VCC=2.3V to 5.5V | 7 | ||
| Propagation delay CP to Q, Q̄ | tpd | 1.5 | 13.4 | ns | VCC=1.65V to 1.95V; Tamb=-40℃ to +105℃ | 9 | |
| Propagation delay CP to Q, Q̄ | tpd | 1 | 7.1 | ns | VCC=2.3V to 2.7V; Tamb=-40℃ to +105℃ | 9 | |
| Propagation delay CP to Q, Q̄ | tpd | 1 | 5.9 | ns | VCC=3.0V to 3.6V; Tamb=-40℃ to +105℃ | 9 | |
| Propagation delay CP to Q, Q̄ | tpd | 1 | 4.1 | ns | VCC=4.5V to 5.5V; Tamb=-40℃ to +105℃ | 9 | |
| Pulse width CP HIGH or LOW | tW | 6.2 | ns | VCC=1.65V to 1.95V | 9 | ||
| Pulse width CP HIGH or LOW | tW | 2.7 | ns | VCC=2.3V to 2.7V | 9 | ||
| Pulse width CP HIGH or LOW | tW | 2 | ns | VCC=4.5V to 5.5V | 9 | ||
| Set-up time D to CP | tsu | 2.9 | ns | VCC=1.65V to 1.95V | 10 | ||
| Set-up time D to CP | tsu | 1.7 | ns | VCC=2.3V to 2.7V | 10 | ||
| Set-up time D to CP | tsu | 1.3 | ns | VCC=3.0V to 3.6V | 10 | ||
| Set-up time D to CP | tsu | 1.1 | ns | VCC=4.5V to 5.5V | 10 | ||
| Maximum frequency CP | fmax | 80 | MHz | VCC=1.65V to 1.95V | 10 | ||
| Maximum frequency CP | fmax | 175 | MHz | VCC=2.3V to 2.7V | 10 | ||
| Maximum frequency CP | fmax | 200 | MHz | VCC=4.5V to 5.5V | 10 | ||
| Input capacitance | CI | 4 | pF | 6 | |||
| Power dissipation capacitance | CPD | 15 | pF | VCC=3.3V; VI=GND to VCC | 9 |
CAD (KiCad official)
- Symbol:
AIP74LVC2G74YA8.TR - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
aip74lvc2g74ya8-tr-etched.step/aip74lvc2g74ya8-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip74lvc2g74ya8-tr.step/aip74lvc2g74ya8-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I-core Elec datasheet (15 pp, sha256
59eed954b5a1a5e4, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).