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SI3430DV-T1-GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, TSOP-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSI3430DV-T1-GE3
Vishay Intertech · MOSFETs · TSOP-6
SI3430DV-T1-GE3 from Vishay Intertech, in a TSOP-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | passive | Drain of the N-channel MOSFET, electrically common with pins 2, 5 and 6, with VDS rated 100 V (absolute maximum). |
| 2 | D | passive | Drain of the N-channel MOSFET, electrically common with pins 1, 5 and 6, with VDS rated 100 V (absolute maximum). |
| 3 | G | input | Gate of the N-channel MOSFET, with gate-source voltage limited to ±20 V per the absolute maximum ratings. |
| 4 | S | passive | Source of the N-channel MOSFET, with continuous source (diode conduction) current IS of 1.7 A at 5 s and 1 A in steady state. |
| 5 | D | passive | Drain of the N-channel MOSFET, electrically common with pins 1, 2 and 6, with VDS rated 100 V (absolute maximum). |
| 6 | D | passive | Drain of the N-channel MOSFET, electrically common with pins 1, 2 and 5, with VDS rated 100 V (absolute maximum). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | TSOP-6 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS | 100 | V | TA = 25 °C; 5 s column | 1 | ||
| Gate-source voltage | VGS | -20 | 20 | V | TA = 25 °C; 5 s column | 1 | |
| Continuous drain current | ID | 2.4 | A | TJ = 175 °C, TA = 25 °C; 5 s column | 1 | ||
| Continuous drain current | ID | 1.8 | A | TJ = 175 °C, TA = 25 °C; steady state column | 1 | ||
| Continuous drain current | ID | 1.7 | A | TJ = 175 °C, TA = 85 °C; 5 s column | 1 | ||
| Continuous drain current | ID | 1.3 | A | TJ = 175 °C, TA = 85 °C; steady state column | 1 | ||
| Pulsed drain current | IDM | 8 | A | 5 s column | 1 | ||
| Avalanche current | IAR | 6 | A | L = 0.1 mH; 5 s column | 1 | ||
| Repetitive avalanche energy | EAR | 1.8 | mJ | duty cycle ≤ 1 %; 5 s column | 1 | ||
| Continuous source current (diode conduction) | IS | 1.7 | A | 5 s column | 1 | ||
| Continuous source current (diode conduction) | IS | 1 | A | steady state column | 1 | ||
| Maximum power dissipation | PD | 2 | W | TA = 25 °C; 5 s column | 1 | ||
| Maximum power dissipation | PD | 1.14 | W | TA = 25 °C; steady state column | 1 | ||
| Maximum power dissipation | PD | 1 | W | TA = 85 °C; 5 s column | 1 | ||
| Maximum power dissipation | PD | 0.59 | W | TA = 85 °C; steady state column | 1 | ||
| Operating junction and storage temperature range | TJ, Tstg | -55 | 150 | °C | 5 s column | 1 | |
| Maximum junction-to-ambient | RthJA | 45 | 62.5 | °C/W | t ≤ 5 s | 1 | |
| Maximum junction-to-ambient | RthJA | 90 | 110 | °C/W | Steady state | 1 | |
| Maximum junction-to-foot (drain) | RthJF | 25 | 30 | °C/W | Steady state | 1 | |
| Gate threshold voltage | VGS(th) | 2 | 4.2 | V | VDS = VDS, ID = 250 μA | 2 | |
| Gate-body leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 | |
| Zero gate voltage drain current | IDSS | 1 | μA | VDS = 80 V, VGS = 0 V | 2 | ||
| Zero gate voltage drain current | IDSS | 25 | μA | VDS = 80 V, VGS = 0 V, TJ = 85 °C | 2 | ||
| On-state drain current | ID(on) | 8 | A | VDS ≥ 5 V, VGS = 10 V | 2 | ||
| Drain-source on-state resistance | RDS(on) | 0.148 | 0.17 | Ω | VGS = 10 V, ID = 2.4 A | 2 | |
| Drain-source on-state resistance | RDS(on) | 0.16 | 0.185 | Ω | VGS = 6 V, ID = 2.3 A | 2 | |
| Diode forward voltage | VSD | 0.8 | 1.2 | V | IS = 1.7 A, VGS = 0 V | 2 | |
| Total gate charge | Qg | 5.5 | 8.2 | nC | VDS = 50 V, VGS = 10 V, ID = 2.4 A | 2 | |
| Gate resistance | Rg | 1 | 4 | Ω | 2 | ||
| Turn-on delay time | td(on) | 9 | 20 | ns | VDD = 50 V, RL = 50 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Rise time | tr | 11 | 20 | ns | VDD = 50 V, RL = 50 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Turn-off delay time | td(off) | 16 | 30 | ns | VDD = 50 V, RL = 50 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Fall time | tf | 9 | 20 | ns | VDD = 50 V, RL = 50 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Source-drain reverse recovery time | trr | 50 | 80 | ns | IF = 1.7 A, di/dt = 100 A/μs | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | pins 1,2,5, and 6. The copper plane connects the drain pins | 7 |
CAD (KiCad official)
- Symbol:
SI3430DV-T1-GE3 - Footprint:
Package_SO:TSOP-6_1.65x3.05mm_P0.95mm - 3D model: TSOP-6 (KiCad packages3D, STEP)
- 3D model files:
si3430dv-t1-ge3-etched.step/si3430dv-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si3430dv-t1-ge3.step/si3430dv-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (10 pp, sha256
ddfb0b23b070a966, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).