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2EDN8524FXTMA1

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Infineon Technologies Gate Drivers, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Contents

README

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2EDN8524FXTMA1

Infineon Technologies · Gate Drivers · TSSOP-8

2EDN8524FXTMA1 from Infineon Technologies, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ENA input Enable input channel A; if ENA is high or left open, OUTA is controlled by INA, and ENA low causes OUTA low.
2 INA input Input signal channel A, controlling OUTA; the 2EDN8524F is the direct (non-inverting) input version.
3 GND power_in Ground.
4 INB input Input signal channel B, controlling OUTB; the 2EDN8524F is the direct (non-inverting) input version.
5 OUTB output Low-impedance driver output channel B with source and sink capability.
6 VDD power_in Positive supply voltage with an operating range of 4.5 V/8.6V to 20 V.
7 OUTA output Low-impedance driver output channel A with source and sink capability.
8 ENB input Enable input channel B; if ENB is high or left open, OUTB is controlled by INB, and ENB low causes OUTB low.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package TSSOP-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive supply voltage VVDD -0.3 22 V 13
Voltage at pins INA, INB, ENA, ENB VIN -10 22 V 13
Voltage at pins OUTA, OUTB VOUT -0.3 V Note 1: voltage spikes from reverse current peaks allowed; max printed as VVDD+0.3 13
Voltage at pins OUTA, OUTB, repetitive pulse VOUT -2 V Repetitive pulse <200ns; max printed as VVDD+0.3 13
Reverse current peak at pins OUTA, OUTB ISNKREV / ISRCREV -5 5 A Apk < 500ns 13
Junction temperature TJ -40 150 °C 13
Storage temperature TS -55 150 °C 13
ESD capability (CDM) VESD 1.5 kV Charged Device Mode (CDM), JESD22-C101 13
ESD capability (HBM) VESD 2.5 kV Human Body Model (HBM), JESD22-A114 13
Supply voltage VVDD 4.5 20 V Min. defined by UVLO 14
Logic input voltage VIN -5 20 V 14
Junction temperature (operating range) TJ -40 150 °C 14
VDD quiescent current IVDDQU1 0.5 0.7 1.2 mA OUT = high, VVDD= 12 V 15
VDD quiescent current IVDDQU2 0.3 0.48 0.7 mA OUT = low, VVDD= 12 V 15
Undervoltage Lockout (UVLO) turn on threshold, standard and superjunction MOSFET version UVLOON 7.4 8 8.6 V 15
Undervoltage Lockout (UVLO) turn off threshold, standard and superjunction MOSFET version UVLOOFF 6.5 7 7.5 V 15
Input voltage threshold for transition LH VINH 1.98 2.1 2.2 V 15
Input voltage threshold for transition HL VINL 0.95 1.02 1.1 V 15
High Level (Sourcing) Output Resistance RONSRC 0.35 0.7 1.2 Ω ISRC = 50mA 16
Low Level (Sinking) Output Resistance RONSNK 0.28 0.55 1 Ω ISNK = 50mA 16
Input/Enable to output propagation delay, low to high TPDlh 15 17 23 ns CLOAD= 1.8 nF, VVDD= 12 V 16
Input/Enable to output propagation delay, high to low TPDhl 15 19 23 ns CLOAD= 1.8 nF, VVDD= 12 V 16
Input/Enable to output propagation delay mismatch between the two channels on the same IC delta tPD 2 ns 16
Rise Time TRISE 5.3 10 ns CLOAD= 1.8 nF, VVDD= 12 V 16
Fall Time TFAll 4.5 10 ns CLOAD= 1.8 nF, VVDD= 12 V 16
Minimum input pulse width that changes output state TPW 6 10 ns CLOAD= 1.8 nF, VVDD= 12 V 16
UVLO threshold hysteresis, standard and superjunction MOSFET version UVLOHYS 1 V 15
Input pull up resistor RINH 400 kΩ Inputs with initial high logic level 15
Input pull down resistor RINL 100 kΩ Inputs with initial low logic level 15
High Level (Sourcing) Output Current ISRCPEAK 5 A Active limited by design at approx. 6.5 Apk; not subject to production test 16
Low Level (Sinking) Output Current ISNKPEAK -5 A Active limited by design at approx. -6.5 Apk; not subject to production test 16
Thermal resistance junction-ambient RthJA25 125 K/W PG-DSO-8-60, Tamb=25°C 13
Thermal resistance junction-case (top) RthJC25 66 K/W PG-DSO-8-60, Tamb=25°C 13
Thermal resistance junction-board RthJB25 62 K/W PG-DSO-8-60, Tamb=25°C 13
Characterization parameter junction-top ΨthJC25 16 K/W PG-DSO-8-60, Tamb=25°C 13
Characterization parameter junction-board ΨthJB25 55 K/W PG-DSO-8-60, Tamb=25°C 13

CAD (KiCad official)

  • Symbol: 2EDN8524FXTMA1
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: 2edn8524fxtma1-etched.step / 2edn8524fxtma1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 2edn8524fxtma1.step / 2edn8524fxtma1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (31 pp, sha256 a22bd5363b44c8ae, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF