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PIC24FJ128GA010-I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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PIC24FJ128GA010-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-100(14x14)

PIC24FJ128GA010-I from Microchip Tech, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RG15 bidirectional PORTG digital I/O with Schmitt Trigger input.
2 VDD power_in Positive supply for peripheral digital logic and I/O pins.
3 PMD5/RE5 bidirectional PORTE digital I/O or Parallel Master Port data bit 5 (ST/TTL).
4 PMD6/RE6 bidirectional PORTE digital I/O or Parallel Master Port data bit 6 (ST/TTL).
5 PMD7/RE7 bidirectional PORTE digital I/O or Parallel Master Port data bit 7 (ST/TTL).
6 T2CK/RC1 bidirectional PORTC digital I/O or Timer2 external clock input.
7 T3CK/RC2 bidirectional PORTC digital I/O or Timer3 external clock input.
8 T4CK/RC3 bidirectional PORTC digital I/O or Timer4 external clock input.
9 T5CK/RC4 bidirectional PORTC digital I/O or Timer5 external clock input.
10 RG6/SCK2/CN8/PMA5 bidirectional PORTG digital I/O, SPI2 serial clock, interrupt-on-change input CN8 or PMP address bit 5.
11 RG7/SDI2/CN9/PMA4 bidirectional PORTG digital I/O, SPI2 serial data input, interrupt-on-change input CN9 or PMP address bit 4.
12 RG8/SDO2/CN10/PMA3 bidirectional PORTG digital I/O, SPI2 serial data output, interrupt-on-change input CN10 or PMP address bit 3.
13 MCLR input Master Clear (device Reset) input; brought low to cause a Reset (Schmitt Trigger).
14 RG9/SS2/CN11/PMA2 bidirectional PORTG digital I/O, SPI2 slave select/frame select, interrupt-on-change input CN11 or PMP address bit 2.
15 VSS power_in Ground reference for logic and I/O pins.
16 VDD power_in Positive supply for peripheral digital logic and I/O pins.
17 TMS/RA0 bidirectional PORTA digital I/O or JTAG Test Mode Select input.
18 INT1/RE8 bidirectional PORTE digital I/O or external interrupt 1 input.
19 INT2/RE9 bidirectional PORTE digital I/O or external interrupt 2 input.
20 RB5/AN5/C1IN+/CN7 bidirectional PORTB digital I/O, A/D analog input 5, comparator 1 positive input or interrupt-on-change CN7.
21 RB4/AN4/C1IN-/CN6 bidirectional PORTB digital I/O, A/D analog input 4, comparator 1 negative input or interrupt-on-change CN6.
22 RB3/AN3/C2IN+/CN5 bidirectional PORTB digital I/O, A/D analog input 3, comparator 2 positive input or interrupt-on-change CN5.
23 RB2/AN2/C2IN-/SS1/CN4 bidirectional PORTB digital I/O, A/D analog input 2, comparator 2 negative input, SPI1 slave select or CN4.
24 PGC1/EMUC1/AN1/CN3/RB1 bidirectional PORTB digital I/O, A/D analog input 1, ICSP programming clock 1, emulator clock 1 or CN3.
25 PGD1/EMUD1/AN0/CN2/RB0 bidirectional PORTB digital I/O, A/D analog input 0, ICSP programming data 1, emulator data 1 or CN2.
26 PGC2/EMUC2/AN6/OCFA/RB6 bidirectional PORTB digital I/O, A/D analog input 6, ICSP programming clock 2, emulator clock 2 or Output Compare Fault A input.
27 PGD2/EMUD2/AN7/RB7 bidirectional PORTB digital I/O, A/D analog input 7, ICSP programming data 2 or emulator data 2.
28 RA9/VREF-/PMA7 bidirectional PORTA digital I/O, A/D and comparator low reference voltage input or PMP address bit 7.
29 RA10/VREF+/PMA6 bidirectional PORTA digital I/O, A/D and comparator high reference voltage input or PMP address bit 6.
30 AVDD power_in Positive supply for analog modules; must always be connected.
31 AVSS power_in Ground reference for analog modules; must always be connected.
32 RB8/AN8/C1OUT bidirectional PORTB digital I/O, A/D analog input 8 or comparator 1 output.
33 RB9/AN9/C2OUT bidirectional PORTB digital I/O, A/D analog input 9 or comparator 2 output.
34 RB10/AN10/CVREF/PMA13 bidirectional PORTB digital I/O, A/D analog input 10, comparator voltage reference output or PMP address bit 13.
35 RB11/AN11/PMA12 bidirectional PORTB digital I/O, A/D analog input 11 or PMP address bit 12.
36 VSS power_in Ground reference for logic and I/O pins.
37 VDD power_in Positive supply for peripheral digital logic and I/O pins.
38 TCK/RA1 bidirectional PORTA digital I/O or JTAG Test Clock/programming clock input.
39 U2RTS/BCLK2/RF13 bidirectional PORTF digital I/O, UART2 IrDA baud clock or UART2 request-to-send output.
40 U2CTS/RF12 bidirectional PORTF digital I/O or UART2 clear-to-send input.
41 RB12/AN12/PMA11 bidirectional PORTB digital I/O, A/D analog input 12 or PMP address bit 11.
42 RB13/AN13/PMA10 bidirectional PORTB digital I/O, A/D analog input 13 or PMP address bit 10.
43 RB14/AN14/PMA1 bidirectional PORTB digital I/O, A/D analog input 14 or PMP address bit 1 (ST/TTL).
44 RB15/AN15/OCFB/PMA0/CN12 bidirectional PORTB digital I/O, A/D analog input 15, Output Compare Fault B input, PMP address bit 0 or CN12.
45 VSS power_in Ground reference for logic and I/O pins.
46 VDD power_in Positive supply for peripheral digital logic and I/O pins.
47 U1CTS/CN20/RD14 bidirectional PORTD digital I/O, interrupt-on-change CN20 or UART1 clear-to-send input.
48 U1RTS/BCLK1/CN21/RD15 bidirectional PORTD digital I/O, interrupt-on-change CN21, UART1 request-to-send output or UART1 IrDA baud clock.
49 RF4/CN17/U2RX/PMA9 bidirectional PORTF digital I/O, interrupt-on-change CN17, UART2 receive input or PMP address bit 9.
50 RF5/CN18/U2TX/PMA8 bidirectional PORTF digital I/O, interrupt-on-change CN18, UART2 transmit output or PMP address bit 8.
51 U1TX/RF3 bidirectional PORTF digital I/O or UART1 transmit output.
52 U1RX/RF2 bidirectional PORTF digital I/O or UART1 receive input.
53 SDO1/RF8 bidirectional PORTF digital I/O or SPI1 serial data output.
54 SDI1/RF7 bidirectional PORTF digital I/O or SPI1 serial data input.
55 SCK1/INT0/RF6 bidirectional PORTF digital I/O, SPI1 serial clock output or external interrupt 0 input.
56 SDA1/RG3 bidirectional PORTG digital I/O or I2C1 data input/output.
57 SCL1/RG2 bidirectional PORTG digital I/O or I2C1 clock input/output.
58 SCL2/RA2 bidirectional PORTA digital I/O or I2C2 clock input/output.
59 SDA2/RA3 bidirectional PORTA digital I/O or I2C2 data input/output.
60 TDI/RA4 bidirectional PORTA digital I/O or JTAG Test Data/programming data input.
61 TDO/RA5 bidirectional PORTA digital I/O or JTAG Test Data output.
62 VDD power_in Positive supply for peripheral digital logic and I/O pins.
63 OSC1/CLKI/RC12 input Main oscillator input connection, main clock input or PORTC digital I/O RC12.
64 OSC2/CLKO/RC15 bidirectional Main oscillator output connection, system clock output or PORTC digital I/O RC15.
65 VSS power_in Ground reference for logic and I/O pins.
66 INT3/RA14 bidirectional PORTA digital I/O or external interrupt 3 input.
67 INT4/RA15 bidirectional PORTA digital I/O or external interrupt 4 input.
68 IC1/RTCC/RD8 bidirectional PORTD digital I/O, input capture 1 or real-time clock alarm output.
69 IC2/RD9 bidirectional PORTD digital I/O or input capture 2.
70 IC3/PMCS2/RD10 bidirectional PORTD digital I/O, input capture 3 or PMP chip select 2 strobe/address bit 15.
71 IC4/PMCS1/RD11 bidirectional PORTD digital I/O, input capture 4 or PMP chip select 1 strobe/address bit 14.
72 OC1/RD0 bidirectional PORTD digital I/O or output compare/PWM 1 output.
73 SOSCI/CN1/RC13 bidirectional PORTC digital I/O, secondary oscillator/Timer1 clock input or interrupt-on-change CN1.
74 SOSCO/T1CK/CN0/RC14 bidirectional PORTC digital I/O, secondary oscillator output, Timer1 clock input or interrupt-on-change CN0.
75 VSS power_in Ground reference for logic and I/O pins.
76 OC2/RD1 bidirectional PORTD digital I/O or output compare/PWM 2 output.
77 OC3/RD2 bidirectional PORTD digital I/O or output compare/PWM 3 output.
78 RD3/OC4/PMBE bidirectional PORTD digital I/O, output compare/PWM 4 output or PMP byte enable strobe.
79 IC5/RD12 bidirectional PORTD digital I/O or input capture 5.
80 CN19/RD13 bidirectional PORTD digital I/O or interrupt-on-change CN19.
81 RD4/OC5/PMWR/CN13 bidirectional PORTD digital I/O, output compare/PWM 5 output, PMP write strobe or interrupt-on-change CN13.
82 PMRD/CN14/RD5 bidirectional PORTD digital I/O, PMP read strobe or interrupt-on-change CN14.
83 CN15/RD6 bidirectional PORTD digital I/O or interrupt-on-change CN15.
84 CN16/RD7 bidirectional PORTD digital I/O or interrupt-on-change CN16.
85 VDDCORE/VDDCAP power_in Core logic supply when regulator is disabled, or external filter capacitor connection (low-ESR, 10 µF to ground, not tied to VDD) when regulator is enabled.
86 ENVREG input Enable for on-chip voltage regulator; tie to VDD to enable or to ground to disable.
87 RF0 bidirectional PORTF digital I/O with Schmitt Trigger input.
88 RF1 bidirectional PORTF digital I/O with Schmitt Trigger input.
89 RG1 bidirectional PORTG digital I/O with Schmitt Trigger input.
90 RG0 bidirectional PORTG digital I/O with Schmitt Trigger input.
91 RA6 bidirectional PORTA digital I/O with Schmitt Trigger input.
92 RA7 bidirectional PORTA digital I/O with Schmitt Trigger input.
93 PMD0/RE0 bidirectional PORTE digital I/O or Parallel Master Port data bit 0 (ST/TTL).
94 PMD1/RE1 bidirectional PORTE digital I/O or Parallel Master Port data bit 1 (ST/TTL).
95 RG14 bidirectional PORTG digital I/O with Schmitt Trigger input.
96 RG12 bidirectional PORTG digital I/O with Schmitt Trigger input.
97 RG13 bidirectional PORTG digital I/O with Schmitt Trigger input.
98 PMD2/RE2 bidirectional PORTE digital I/O or Parallel Master Port data bit 2 (ST/TTL).
99 PMD3/RE3 bidirectional PORTE digital I/O or Parallel Master Port data bit 3 (ST/TTL).
100 PMD4/RE4 bidirectional PORTE digital I/O or Parallel Master Port data bit 4 (ST/TTL).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -40 85 °C 217
Storage temperature -65 150 °C 217
Voltage on VDD with respect to VSS VDD -0.3 4 V 217
Voltage on any combined analog and digital pin and MCLR -0.3 V with respect to VSS, max is VDD + 0.3V 217
Voltage on any digital only pin -0.3 6 V with respect to VSS 217
Voltage on VDDCORE VDDCORE -0.3 2.8 V with respect to VSS 217
Maximum output current sunk by any I/O pin 25 mA 217
Maximum output current sourced by any I/O pin 25 mA 217
Operating Junction Temperature Range TJ -40 125 °C 218
Operating Ambient Temperature Range TA -40 85 °C 218
Supply Voltage (regulator enabled) VDD 3.6 V Regulator is enabled; min is VBOR 218
Supply Voltage (regulator disabled) VDD 3.6 V Regulator is disabled; min is VDDCORE 218
Core supply voltage VDDCORE 2 2.75 V Regulator is disabled 218
RAM Data Retention Voltage VDR 1.5 V 218
VDD Rise Rate to Ensure Internal POR SVDD 0.05 V/ms 0-3.3V in 0.1s; 0-2.5V in 60 ms 218
Brown-out Reset Voltage VBOR 1.9 2.2 2.5 V Regulator must be enabled 218
Package Thermal Resistance, 14x14x1 mm TQFP θJA 50 °C/W Note 1 218
Operating Current IDD 1.6 4 mA 1 MIPS, 2.5V, -40°C 219
Operating Current IDD 6 12 mA 4 MIPS, 2.5V, -40°C 219
Operating Current IDD 20 32 mA 16 MIPS, 2.5V, -40°C 219
Operating Current LPRC (31 kHz) IDD 200 400 µA +85°C, 2.5V 219
Idle Current IIDLE 0.7 2 mA 1 MIPS, 2.5V, -40°C 220
Idle Current IIDLE 6.8 8 mA 16 MIPS, 2.5V, -40°C 220
Base Power-Down Current IPD 3 25 µA 2.0V, -40°C 221
Base Power-Down Current IPD 120 600 µA 3.6V, +85°C 221
Watchdog Timer Current IWDT 10 25 µA 2.0V, -40°C 221
RTCC + Timer1 w/32 kHz Crystal IRTCC 8 15 µA 2.0V, -40°C 221
Input Low Voltage, I/O Pins with ST Buffer VIL 0.2 V max printed as 0.2 VDD; min VSS 222
Input Low Voltage, I/O Pins with TTL Buffer VIL 0.15 V max printed as 0.15 VDD; min VSS 222
Input Low Voltage, SMBus Buffer VIL 0.8 V SMBus enabled 222
Input High Voltage, ST Buffer Digital Only VIH 0.8 5.5 V min printed as 0.8 VDD 222
CNxx Pull-up Current ICNPU 50 250 400 µA VDD = 3.3V, VPIN = VSS 222
Input Leakage Current, I/O Ports IIL 50 1000 nA Pin at high-impedance, VSS ≤ VPIN ≤ VDD 222
Output Low Voltage, I/O Ports VOL 0.4 V IOL = 8.5 mA, VDD = 3.6V 223
Output High Voltage, I/O Ports VOH 3 V IOH = -3.0 mA, VDD = 3.6V 223
Output High Voltage, I/O Ports VOH 2.4 V IOH = -6.0 mA, VDD = 3.6V 223
Output High Voltage, I/O Ports VOH 1.4 V IOH = -3.0 mA, VDD = 2.0V 223
VDD for Self-Timed Erase/Write VPEW 2.25 3.6 V 225
Flash Characteristic Retention TRETD 20 Year Provided no other specifications are violated 225
Regulator Output Voltage VRGOUT 2.5 V 225
External Filter Capacitor Value CEFC 4.7 10 µF Series resistance < 3 Ohm recommended; < 5 Ohm required. 225
Comparator Input Offset Voltage VIOFF 10 30 mV 226
Comparator Common Mode Rejection Ratio CMRR 55 dB 226
Comparator Response Time TRESP 150 400 ns 226
External CLKI Frequency, EC mode FOSC 32 MHz EC mode; min DC 228
Instruction Cycle Time TCY 62.5 ns 228
PLL Output Frequency Range FSYS 12 32 MHz 229
FRC Accuracy @ 8 MHz FRC -2 2 % +25°C VDD = 3.0 - 3.6V 229
FRC Accuracy @ 8 MHz FRC -5 5 % -40°C ≤ TA ≤ +85°C VDD = 3.0 - 3.6V 229
LPRC @ 31 kHz accuracy -15 15 % -40°C ≤ TA ≤ +85°C VDD = 3.0 - 3.6V 229
A/D Integral Nonlinearity INL 1 2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V 231
A/D Throughput Rate FCNV 500 ksps AVDD > 2.7V 232

CAD (KiCad official)

  • Symbol: PIC24FJ128GA010-I
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: pic24fj128ga010-i-etched.step / pic24fj128ga010-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic24fj128ga010-i.step / pic24fj128ga010-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (258 pp, sha256 bb7c3ecb1fafd326, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF