TLV320AIC1110PBSR from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MBIAS	output	Microphone bias supply output with no decoupling capacitors.
2	MIC1P	input	MIC1 non-inverting (+) differential microphone input.
3	MIC1N	input	MIC1 inverting (-) differential microphone input.
4	MIC2P	input	MIC2 non-inverting (+) differential microphone input.
5	MIC2N	input	MIC2 inverting (-) differential microphone input.
6	REXT	bidirectional	Internal reference current setting terminal that requires a precision 100-kΩ resistor and no filtering capacitors.
7	MUXIN	input	Analog MUX input to the 2-channel auxiliary analog switch.
8	AVSS	power_in	Analog negative power supply, used as the ground connection.
9	MUXOUT1	input	Analog MUX output of the auxiliary analog switch.
10	MUXOUT2	input	Analog MUX output of the auxiliary analog switch.
11	SDA	bidirectional	I2C-bus serial address/data line, open-drain, requiring a pullup resistor to VDD (typically 10 kΩ for 100 kHz).
12	SCL	input	I2C-bus serial clock input used to synchronize data transfer to and from the PCM codec.
13	DVDD	power_in	Digital positive power supply, 2.7 V to 3.3 V.
14	DVSS	power_in	Digital negative power supply, used as ground.
15	PCMI	input	Receive PCM data input.
16	PCMO	output	Transmit PCM data output.
17	PCMCLK	input	PCM data clock input.
18	PCMSYN	input	PCM frame sync input.
19	BUZZCON	output	Pulse-density modulated buzzer output to drive an external buzzer driver.
20	PWRUPSEL	input	Selects the power-up default mode; tying it to VCC enables voice-mode-only general-purpose PCM codec operation.
21	RESET	input	Active-low reset input.
22	MCLK	input	Master system clock input at 2.048 MHz, digital.
23	VSS	power_in	Ground return for the bandgap internal reference, used as a ground connection.
24	PLLVSS	power_in	PLL negative power supply.
25	PLLVDD	power_in	PLL digital positive power supply, 2.7 V to 3.3 V.
26	EARVSS	power_in	Analog negative power supply for the earphone amplifiers.
27	EAR1ON	output	Earphone 1 amplifier differential output (-); load impedance 8 to 32 Ω between EAR1OP and EAR1ON.
28	EARVDD	power_in	Analog positive power supply for the earphone amplifiers, 2.7 V to 3.3 V.
29	EAR1OP	output	Earphone 1 amplifier differential output (+); load impedance 8 to 32 Ω between EAR1OP and EAR1ON.
30	EARVSS	power_in	Analog negative power supply for the earphone amplifiers.
31	EAR2O	output	Earphone 2 single-ended amplifier output; load impedance 32 Ω.
32	AVDD	power_in	Analog positive power supply, 2.7 V to 3.3 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-32(5x5)
Category	Interface
Pins	32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	AVDD, DVDD, PLLVDD, EARVDD	2.7		3.3	V		9
Load impedance between EAR1OP and EAR1ON	RL	8		32	Ω		9
Load impedance for EAR2	RL			32	Ω	EAR2OP-RL	9
Operating free-air temperature	TA	-40		85	°C		9
Supply voltage range	AVDD, DVDD, PLLVDD, EARVDD	-0.5		3.6	V		9
Output voltage range	VO	-0.5		3.6	V		9
Input voltage range	VI	-0.5		3.6	V		9
Operating free air temperature range (industrial temperature)		-40		85	°C		9
Storage temperature range, testing		-65		150	°C		9
Lead temperature				260	°C	1,6 mm from case for 10 seconds	9
Supply current, operating, EAR1 selected	IDD	4.5		6	mA	MicBias disabled	9
Supply current, operating, EAR2 selected	IDD	4.5		6	mA	MicBias disabled	9
Supply current, power down, Reg 6 bit 7 = 1	IDD	2		10	µA	room temperature, VDD = 3 V, MClk not present	9
Supply current, power down, Reg 6 bit 7 = 0	IDD	10		30	µA	room temperature, VDD = 3 V, MClk not present	9
Power-up time from power down	ton(i)	5		10	ms		9
Low-level output voltage PCMO (BUZZCON)	VOL			0.25	V	IOL = 3.2 mA, VDD = 3 V	10
High-level input current, any digital input	IIH			10	µA	VI = VDD	10
Low-level input current, any digital input	IIL			10	µA	VI = VSS	10
Input capacitance	Ci			10	pF		10
Output capacitance	Co			20	pF		10
Load impedance (BUZZCON)	RL			5	kΩ		10
Input offset voltage at MIC1N, MIC2N	VIO	-5		5	mV	See Note 4	10
Input bias current at MIC1N, MIC2N	IIB	-300		300	nA		10
Input capacitance at MIC1N, MIC2N	Ci			5	pF	at MIC1N, MIC2N	10
Microphone input referred noise, psophometrically weighted	Vn	3		4.7	µVrms	MIC amp 1 gain = 23.5 dB; MIC amp 2 gain = 0 dB	10
Output source current, MBIAS	IOmax	1		1.2	mA		10
Microphone bias supply voltage	V(mbias)	2.3	2.5	2.65	V	see Note 5	10
Microphone mute				-80	dB		10
Input impedance, fully differential		35	60	100	kΩ	Fully differential	10
Earphone AMP1 output power, 8-Ω load		161		200	mW	VDD = 2.7 V, fully differential, 8-Ω load, 3-dBm0 output, volume control = -3 dB, RXPGA = -4 dB level	11
Earphone AMP1 output power, 16-Ω load		128		160	mW	VDD = 2.7 V, fully differential, 16-Ω load, 3-dBm0 output, volume control = -3 dB, RXPGA = -2 dB level	11
Earphone AMP1 output power, 32-Ω load		81		100	mW	VDD = 2.7 V, fully differential, 32-Ω load, 3-dBm0 output, volume control = -3 dB, RXPGA = -1 dB level	11
Earphone AMP2 output power		10		12.5	mW	VDD = 2.7 V, single-ended, 32-Ω load, 3-dBm0 output	11
Output offset voltage at EAR1	VOO	-30		30	mV	Fully differential	11
Maximum output current for EAR1 (rms), 8-Ω load	I max	141		178	mA	3-dBm0 input, 8-Ω load	11
Maximum output current for EAR1 (rms), 16-Ω load	I max	90		112	mA	3-dBm0 input, 16-Ω load	11
Maximum output current for EAR1 (rms), 32-Ω load	IOmax	50		63	mA	3-dBm0 input, 32-Ω load	11
Maximum output current for EAR2 (rms)		17.7		22.1	mA	3-dBm0 input	11
Earphone mute				-80	dB		11
Absolute gain error, transmit		-1		1	dB	0-dBm0 input signal, VDD ±10%	11
Gain error with input level relative to gain at -10 dBm0, transmit		-0.5		0.5	dB	MIC1N, MIC1P to PCMO at 3 dBm0 to -30 dBm0; slope filter bypassed	11
Gain error with input level relative to gain at -10 dBm0, transmit		-1		1	dB	MIC1N, MIC1P to PCMO at -31 dBm0 to -45 dBm0; slope filter bypassed	11
Gain error with input level relative to gain at -10 dBm0, transmit		-1.2		1.2	dB	MIC1N, MIC1P to PCMO at -46 dBm0 to -55 dBm0; slope filter bypassed	11
Overload signal level (3 dBm0), normal mode				124	mV	Differential, normal mode	11
Transmit reference-signal level (0 dB)				87.5	mVpp	Differential	11
Gain relative to 1020 Hz, internal high-pass filter disabled, below 100 Hz		-0.5		0.5	dB	fMIC1 or fMIC2 <100 Hz; slope filter bypassed; MCLK = 2.048 MHz	12
Gain relative to 1020 Hz, internal high-pass filter disabled, 200 Hz		-0.5		0.5	dB	fMIC1 or fMIC2 = 200 Hz; slope filter bypassed; MCLK = 2.048 MHz	12
Gain relative to 1020 Hz, internal high-pass filter disabled, 300 Hz to 3 kHz		-0.5		0.5	dB	fMIC1 or fMIC2 = 300 Hz to 3 kHz; slope filter bypassed; MCLK = 2.048 MHz	12
Gain relative to 1020 Hz, internal high-pass filter disabled, 3.4 kHz		-1.5		0	dB	fMIC1 or fMIC2 = 3.4 kHz; slope filter bypassed; MCLK = 2.048 MHz	12
Overload signal level (3 dB), EAR1, 8-Ω load				3.2	Vpp	8-Ω load RXPGA = -4 dB	14
Overload signal level (3 dB), EAR1, 16-Ω load				4.05	Vpp	16-Ω load RXPGA = -4 dB	14
Overload signal level (3 dB), EAR1, 32-Ω load				4.54	Vpp	32-Ω load RXPGA = -4 dB	14
Absolute gain error, receive EAR1		-1		1	dB	0 dBm0 input signal, VDD ±10%	14
Supply voltage rejection, transmit channel		-86		-70	dB	MIC1N, MIC1P = 0 V, VDD = 3 Vdc + 100 mVpeak to peak, f = 0 to 50 kHz	16
PCMCLK clock period, 2.048-MHz CLK	tc(PCMCLK)	156	488	512	ns	2.048-MHz CLK	17
Propagation delay PCMCLK bit 1 high to PCMO bit 1 valid	tpd1			35	ns	CL(max) = 10 pF	18
Propagation delay PCMCLK high to PCMO valid, bits 2 to n	tpd2			35	ns	CL(max) = 10 pF	18
Propagation delay PCMCLK bit n low to PCMO bit n Hi-Z	tpd3			30	ns	CL(max) = 10 pF	18
SCL clock frequency	SCL			400	kHz	I2C bus	18

CAD (KiCad official)

Symbol: TLV320AIC1110PBSR
Footprint: Package_QFP:TQFP-32_5x5mm_P0.5mm
3D model: TQFP-32(5x5) (KiCad packages3D, STEP)
3D model files: tlv320aic1110pbsr-etched.step / tlv320aic1110pbsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv320aic1110pbsr.step / tlv320aic1110pbsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (41 pp, sha256 a76f804992dacb8e, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TLV320AIC1110PBSR

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