component
STM32U575RGT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32U575RGT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32U575RGT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM in VBAT mode, functional down to VBOR_VBAT min. |
| 2 | PC13 | bidirectional | FT GPIO supplied through the VSW power switch, which sinks only 3 mA shared with PC14/PC15; output speed must not exceed 2 MHz at 30 pF and it must not drive current sources such as LEDs. |
| 3 | PC14-OSC32_IN | bidirectional | FT_o I/O with LSE oscillator input OSC32_IN, supplied through the VSW power switch (3 mA shared with PC13/PC15) and not to be used as a current source. |
| 4 | PC15-OSC32_OUT | bidirectional | FT_o I/O with LSE oscillator output OSC32_OUT, supplied through the VSW power switch (3 mA shared with PC13/PC14) and not to be used as a current source. |
| 5 | PH0-OSC_IN (PH0) | bidirectional | 5 V-tolerant FT I/O whose additional function is HSE oscillator input OSC_IN. |
| 6 | PH1-OSC_OUT (PH1) | bidirectional | 5 V-tolerant FT I/O whose additional function is HSE oscillator output OSC_OUT. |
| 7 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| 8 | PC0 | bidirectional | FT_fha I/O (5 V-tolerant, Fm+ capable, high-speed low-voltage mode, analog switch supplied by VDDA) with alternate functions LPTIM1_IN1, I2C3_SCL (boot), LPUART1_RX, SDMMC1_D5, SAI2_FS_A and analog input ADC1_IN1/ADC4_IN1. |
| 9 | PC1 | bidirectional | FT_fhav I/O (5 V-tolerant, Fm+, high-speed low-voltage, VDDA analog switch, very high-speed) with alternate functions TRACED0, LPTIM1_CH1, SPI2_MOSI, I2C3_SDA (boot), LPUART1_TX, SAI1_SD_A and analog input ADC1_IN2/ADC4_IN2. |
| 10 | PC2 | bidirectional | FT_ha I/O (5 V-tolerant, VDDA analog switch, high-speed low-voltage) with alternate functions LPTIM1_IN2, SPI2_MISO, MDF1_CCK1, OCTOSPIM_P1_IO5, LPGPIO1_P5 and analog input ADC1_IN3/ADC4_IN3. |
| 11 | PC3 | bidirectional | FT_ha I/O (5 V-tolerant, VDDA analog switch, high-speed low-voltage) with alternate functions LPTIM1_ETR, LPTIM3_CH1, SAI1_D1, SPI2_MOSI, OCTOSPIM_P1_IO6, SAI1_SD_A, LPTIM2_ETR and analog input ADC1_IN4/ADC4_IN4. |
| 12 | VSSA | power_in | Analog ground; all voltages are referenced to VSS and this pin must always be connected to the external supply within the permitted range. |
| 13 | VDDA | power_in | Analog supply for the ADC, DAC, OPAMP, COMP and VREFBUF; the external main supply voltage including VDDA is limited to -0.3 V to 4.0 V (absolute maximum). |
| 14 | PA0 | bidirectional | FT_hat I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch) with alternate functions TIM2_CH1, TIM5_CH1, TIM8_ETR, SPI3_RDY, USART2_CTS, UART4_TX, SDMMC2_CMD, AUDIOCLK, and analog input OPAMP1_VINP/ADC1_IN5, WKUP1. |
| 15 | PA1 | bidirectional | FT_hat I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch) with alternate functions LPTIM1_CH2, TIM2_CH2, TIM5_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS/USART2_DE, UART4_RX and analog input OPAMP1_VINM/ADC1_IN6, WKUP3. |
| 16 | PA2 | bidirectional | FT_ha I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch) with alternate functions TIM2_CH3, TIM5_CH3, SPI1_RDY, USART2_TX (boot), LPUART1_TX, UCPD1_FRSTX1, TIM15_CH1 and analog input COMP1_INP3/ADC1_IN7, WKUP4/LSCO. |
| 17 | PA3 | bidirectional | TT_hav I/O (3.6 V-tolerant, high-speed low-voltage, VDDA analog switch, very high-speed) with alternate functions TIM2_CH4, TIM5_CH4, SAI1_CK1, USART2_RX (boot), LPUART1_RX, SAI1_MCLK_A, TIM15_CH2 and analog output OPAMP1_VOUT/ADC1_IN8, WKUP5. |
| 18 | VSS | power_in | Ground pin; must be connected to the external ground within the permitted variation of ground pins (50 mV). |
| 19 | VDD | power_in | Main digital supply pin; the device operates from a 1.71 V to 3.6 V power supply. |
| 20 | PA4 | bidirectional | TT_ha I/O (3.6 V-tolerant, high-speed low-voltage, VDDA analog switch) with alternate functions OCTOSPIM_P1_NCS, SPI1_NSS (boot), SPI3_NSS, USART2_CK, DCMI_HSYNC/PSSI_DE, SAI1_FS_B, LPTIM2_CH1 and analog function ADC1_IN9/ADC4_IN9, DAC1_OUT1, WKUP2. |
| 21 | PA5 | bidirectional | TT_a I/O (3.6 V-tolerant, VDDA analog switch) with alternate functions CSLEEP, TIM2_CH1, TIM2_ETR, TIM8_CH1N, PSSI_D14, SPI1_SCK (boot), USART3_RX, LPTIM2_ETR and analog function ADC1_IN10/ADC4_IN10, DAC1_OUT2, WKUP6. |
| 22 | PA6 | bidirectional | FT_ha I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch) with alternate functions CDSTOP, TIM1_BKIN, TIM3_CH1, TIM8_BKIN, DCMI_PIXCLK/PSSI_PDCK, SPI1_MISO (boot), USART3_CTS, LPUART1_CTS, OCTOSPIM_P1_IO3, TIM16_CH1 and analog input OPAMP2_VINP/ADC1_IN11/ADC4_IN11, WKUP7. |
| 23 | PA7 | bidirectional | FT_fha I/O (5 V-tolerant, Fm+ capable, high-speed low-voltage, VDDA analog switch) with alternate functions SRDSTOP, TIM1_CH1N, TIM3_CH2, TIM8_CH1N, I2C3_SCL, SPI1_MOSI (boot), USART3_TX, OCTOSPIM_P1_IO2, LPTIM2_CH2, TIM17_CH1 and analog input OPAMP2_VINM/ADC1_IN12/ADC4_IN20, WKUP8. |
| 24 | PC4 | bidirectional | FT_ha I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch) with alternate functions USART3_TX and OCTOSPIM_P1_IO7, and analog inputs COMP1_INM2, ADC1_IN13, ADC4_IN22. |
| 25 | PC5 | bidirectional | FT_at I/O (5 V-tolerant, VDDA analog switch, TAMP capable) with alternate functions TIM1_CH4N, SAI1_D3, PSSI_D15, USART3_RX and analog inputs COMP1_INP1, ADC1_IN14, ADC4_IN23, WKUP5, TAMP_IN4/TAMP_OUT5. |
| 26 | PB0 | bidirectional | TT_ha I/O (3.6 V-tolerant, high-speed low-voltage, VDDA analog switch) with alternate functions TIM1_CH2N, TIM3_CH3, TIM8_CH2N, LPTIM3_CH1, SPI1_NSS, USART3_CK, OCTOSPIM_P1_IO1, COMP1_OUT, AUDIOCLK and analog function OPAMP2_VOUT/ADC1_IN15/ADC4_IN18. |
| 27 | PB1 | bidirectional | FT_ha I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch) with alternate functions TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LPTIM3_CH2, MDF1_SDI0, USART3_RTS/USART3_DE, LPUART1_RTS/LPUART1_DE, OCTOSPIM_P1_IO0 and analog input COMP1_INM1/ADC1_IN16/ADC4_IN19, WKUP4. |
| 28 | PB2 | bidirectional | FT_hat I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch) with alternate functions LPTIM1_CH1, TIM8_CH4N, I2C3_SMBA, SPI1_RDY, MDF1_CKI0, OCTOSPIM_P1_DQS, UCPD1_FRSTX1 and analog input COMP1_INP2/ADC1_IN17, WKUP1, RTC_OUT2. |
| 29 | PB10 | bidirectional | FT_fhv I/O (5 V-tolerant, Fm+ capable, high-speed low-voltage, very high-speed) with alternate functions TIM2_CH3, LPTIM3_CH1, I2C4_SCL, I2C2_SCL (boot), SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, OCTOSPIM_P1_CLK, COMP1_OUT, SAI1_SCK_A and wake-up WKUP8. |
| 30 | VCAP | power_out | Output of the internal LDO supplying the core; connect COUT = 4.7 µF or 2 × 2.2 µF ±20% with ESR < 20 mΩ at 3 MHz and rated voltage ≥ 10 V. |
| 31 | VSS | power_in | Ground pin; must be connected to the external ground within the permitted variation of ground pins (50 mV). |
| 32 | VDD | power_in | Main digital supply pin; the device operates from a 1.71 V to 3.6 V power supply. |
| 33 | PB12 | bidirectional | FT_hav I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch, very high-speed) with alternate functions TIM1_BKIN, I2C2_SMBA, SPI2_NSS (boot), MDF1_SDI1, USART3_CK, LPUART1_RTS/LPUART1_DE, TSC_G1_IO1, OCTOSPIM_P1_NCLK, SAI2_FS_A, TIM15_BKIN. |
| 34 | PB13 | bidirectional | FT_fa I/O (5 V-tolerant, Fm+ capable, VDDA analog switch) with alternate functions TIM1_CH1N, LPTIM3_IN1, I2C2_SCL, SPI2_SCK (boot), MDF1_CKI1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SAI2_SCK_A, TIM15_CH1N. |
| 35 | PB14 | bidirectional | FT_fda I/O (5 V-tolerant, Fm+ capable, VDDA analog switch) with alternate functions TIM1_CH2N, LPTIM3_ETR, TIM8_CH2N, I2C2_SDA, SPI2_MISO (boot), MDF1_SDI2, USART3_RTS/USART3_DE, TSC_G1_IO3, SDMMC2_D0, SAI2_MCLK_A, TIM15_CH1; additional function UCPD1_DBCC2 (dead-battery control). |
| 36 | PB15 | bidirectional | FT_c I/O (USB Type-C power delivery function) with alternate functions RTC_REFIN, TIM1_CH3N, LPTIM2_IN2, TIM8_CH3N, SPI2_MOSI (boot), MDF1_CKI2, FMC_NBL1, SDMMC2_D1, SAI2_SD_A, TIM15_CH2; additional UCPD1_CC2 and WKUP7, with a pull-down (Rd 5.1 kΩ) active after reset unless UCPD_DBDIS = 1. |
| 37 | PC6 | bidirectional | FT_a I/O (5 V-tolerant, VDDA analog switch) with alternate functions CSLEEP, TIM3_CH1, TIM8_CH1, MDF1_CKI3, SDMMC1_D0DIR, TSC_G4_IO1, DCMI_D0/PSSI_D0, SDMMC2_D6, SDMMC1_D6, SAI2_MCLK_A. |
| 38 | PC7 | bidirectional | FT_a I/O (5 V-tolerant, VDDA analog switch) with alternate functions CDSTOP, TIM3_CH2, TIM8_CH2, MDF1_SDI3, SDMMC1_D123DIR, TSC_G4_IO2, DCMI_D1/PSSI_D1, SDMMC2_D7, SDMMC1_D7, SAI2_MCLK_B, LPTIM2_CH2. |
| 39 | PC8 | bidirectional | FT_a I/O (5 V-tolerant, VDDA analog switch) with alternate functions SRDSTOP, TIM3_CH3, TIM8_CH3, TSC_G4_IO3, DCMI_D2/PSSI_D2, SDMMC1_D0, LPTIM3_CH1. |
| 40 | PC9 | bidirectional | FT_a I/O (5 V-tolerant, VDDA analog switch) with alternate functions TRACED0, TIM8_BKIN2, TIM3_CH4, TIM8_CH4, DCMI_D3/PSSI_D3, TSC_G4_IO4, OTG_FS_NOE, SDMMC1_D1, LPTIM3_CH2. |
| 41 | PA8 | bidirectional | FT_hv I/O (5 V-tolerant, high-speed low-voltage, very high-speed) with alternate functions MCO, TIM1_CH1, SAI1_CK2, SPI1_RDY, USART1_CK, OTG_FS_SOF, TRACECLK, SAI1_SCK_A, LPTIM2_CH1. |
| 42 | PA9 | bidirectional | FT_u I/O (5 V-tolerant, USB function supplied by VDDUSB) with alternate functions TIM1_CH2, SPI2_SCK, DCMI_D0/PSSI_D0, USART1_TX (boot), SAI1_FS_A, TIM15_BKIN; additional function OTG_FS_VBUS. |
| 43 | PA10 | bidirectional | FT_u I/O (5 V-tolerant, USB function supplied by VDDUSB) with alternate functions CRS_SYNC, TIM1_CH3, LPTIM2_IN2, SAI1_D1, DCMI_D1/PSSI_D1, USART1_RX (boot), OTG_FS_ID, SAI1_SD_A, TIM17_BKIN. |
| 44 | PA11 | bidirectional | FT_u I/O (5 V-tolerant, USB function supplied by VDDUSB) with alternate functions TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, FDCAN1_RX; additional function OTG_FS_DM (boot). |
| 45 | PA12 | bidirectional | FT_u I/O (5 V-tolerant, USB function supplied by VDDUSB) with alternate functions TIM1_ETR, SPI1_MOSI, OCTOSPIM_P2_NCS, USART1_RTS/USART1_DE, FDCAN1_TX; additional function OTG_FS_DP (boot). |
| 46 | PA13 (JTMS/SWDIO) | bidirectional | FT I/O that after reset is configured as the JTMS/SWDIO debug function with an internal pull-up; alternate functions include IR_OUT, OTG_FS_NOE and SAI1_SD_B. |
| 47 | VSS | power_in | Ground pin; must be connected to the external ground within the permitted variation of ground pins (50 mV). |
| 48 | VDDUSB | power_in | Supply for the USB function; included in the external main supply voltage limits of -0.3 V to 4.0 V (absolute maximum). |
| 49 | PA14 (JTCK/SWCLK) | bidirectional | FT I/O that after reset is configured as the JTCK/SWCLK debug function with an internal pull-down; alternate functions include LPTIM1_CH1, I2C1_SMBA, I2C4_SMBA, OTG_FS_SOF and SAI1_FS_B. |
| 50 | PA15 (JTDI) | bidirectional | FT_c I/O that after reset is configured as the JTDI debug function with an internal pull-up and a UCPD pull-down (Rd 5.1 kΩ) that can be disabled with UCPD_DBDIS = 1; alternate functions include TIM2_CH1, USART2_RX, SPI1_NSS, SPI3_NSS, UART4_RTS/UART4_DE and SAI2_FS_B. |
| 51 | PC10 | bidirectional | FT_a I/O (5 V-tolerant, VDDA analog switch) with alternate functions TRACED1, LPTIM3_ETR, ADF1_CCK1, SPI3_SCK, USART3_TX (boot), UART4_TX, TSC_G3_IO2, DCMI_D8/PSSI_D8, SDMMC1_D2, SAI2_SCK_B. |
| 52 | PC11 | bidirectional | FT_ha I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch) with alternate functions LPTIM3_IN1, ADF1_SDI0, DCMI_D2/PSSI_D2, OCTOSPIM_P1_NCS, SPI3_MISO, USART3_RX (boot), UART4_RX, TSC_G3_IO3, UCPD1_FRSTX2, SDMMC1_D3, SAI2_MCLK_B. |
| 53 | PC12 | bidirectional | FT_hav I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch, very high-speed) with alternate functions TRACED3, SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, DCMI_D9/PSSI_D9, LPGPIO1_P10, SDMMC1_CK, SAI2_SD_B. |
| 54 | PD2 | bidirectional | FT I/O (5 V-tolerant) with alternate functions TRACED2, TIM3_ETR, USART3_RTS/USART3_DE, UART5_RX, TSC_SYNC, DCMI_D11/PSSI_D11, LPGPIO1_P7, SDMMC1_CMD, LPTIM4_ETR. |
| 55 | PB3 (JTDO/TRACESWO) | bidirectional | FT_fa I/O (5 V-tolerant, Fm+ capable, VDDA analog switch) with alternate functions JTDO/TRACESWO, TIM2_CH2, LPTIM1_CH1, ADF1_CCK0, I2C1_SDA, SPI1_SCK, SPI3_SCK, USART1_RTS/USART1_DE, CRS_SYNC, SDMMC2_D2, SAI1_SCK_B; additional COMP2_INM2. |
| 56 | PB4 (NJTRST) | bidirectional | FT_fa I/O (5 V-tolerant, Fm+ capable, VDDA analog switch) that after reset is configured with an internal pull-up as NJTRST; alternate functions include LPTIM1_CH2, TIM3_CH1, SPI1_MISO, SPI3_MISO, USART1_CTS, TSC_G2_IO1, SDMMC2_D3, TIM17_BKIN; additional COMP2_INP1. |
| 57 | PB5 | bidirectional | FT_havd I/O (5 V-tolerant, high-speed low-voltage, VDDA analog switch, dead-battery function) with alternate functions LPTIM1_IN1, TIM3_CH2, OCTOSPIM_P1_NCLK, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI (boot), USART1_CK, UART5_CTS, TSC_G2_IO2, COMP2_OUT, SAI1_SD_B, TIM16_BKIN; additional UCPD1_DBCC1 and WKUP6. |
| 58 | PB6 | bidirectional | FT_fa I/O (5 V-tolerant, Fm+ capable, VDDA analog switch) with alternate functions LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL (boot), I2C4_SCL, MDF1_SDI5, USART1_TX, TSC_G2_IO3, DCMI_D5/PSSI_D5, SAI1_FS_B, TIM16_CH1N; additional COMP2_INP2 and WKUP3. |
| 59 | PB7 | bidirectional | FT_fhav I/O (5 V-tolerant, Fm+, high-speed low-voltage, VDDA analog switch, very high-speed) with alternate functions LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA (boot), I2C4_SDA, MDF1_CKI5, USART1_RX, UART4_CTS, TSC_G2_IO4, DCMI_VSYNC/PSSI_RDY, FMC_NL, TIM17_CH1N; additional COMP2_INM1, PVD_IN and WKUP4. |
| 60 | PH3-BOOT0 | bidirectional | FT I/O whose function after reset is the BOOT0 boot-mode selection pin (boot modes are defined in Table 6/Table 7). |
| 61 | PB8 | bidirectional | FT_f I/O (5 V-tolerant, Fm+ capable) with alternate functions TIM4_CH3, SAI1_CK1, I2C1_SCL, MDF1_CCK0, SPI3_RDY, SDMMC1_CKIN, FDCAN1_RX (boot), DCMI_D6/PSSI_D6, SDMMC2_D4, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1; additional WKUP5. |
| 62 | PB9 | bidirectional | FT_f I/O (5 V-tolerant, Fm+ capable) with alternate functions IR_OUT, TIM4_CH4, SAI1_D2, I2C1_SDA, SPI2_NSS, SDMMC1_CDIR, FDCAN1_TX (boot), DCMI_D7/PSSI_D7, SDMMC2_D5, SDMMC1_D5, SAI1_FS_A, TIM17_CH1. |
| 63 | VSS | power_in | Ground pin; must be connected to the external ground within the permitted variation of ground pins (50 mV). |
| 64 | VDD | power_in | Main digital supply pin; the device operates from a 1.71 V to 3.6 V power supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage (VDDSMPS, VDDA, VDDUSB, VBAT, VREF+) | VDDX - VSS | -0.3 | 4 | V | Including VDDSMPS, VDDA, VDDUSB, VBAT, VREF+ | 154 | |
| I/O supply voltage when HSLV = 0 | VDDIOx - VSS | -0.3 | 4 | V | HSLV = 0 | 154 | |
| I/O supply voltage when HSLV = 1 | VDDIOx - VSS | -0.3 | 2.75 | V | HSLV = 1 | 154 | |
| Input voltage on FT_xx pins except FT_c pins | VIN | -0.3 | V | Max = Min(min(VDD, VDDA, VDDUSB, VDDIO2) + 4.0, 6.0); footnotes 5, 6 | 154 | ||
| Input voltage on FT_c pins | VIN | -0.3 | 5.5 | V | 154 | ||
| Input voltage on any other pins | VIN | -0.3 | 4 | V | 154 | ||
| Allowed voltage difference for VREF+ > VDDA | VREF+ - VDDA | 0.4 | V | VREF+ > VDDA | 154 | ||
| Variations between different VDDx power pins of the same domain | /ΔVDDx/ | 50 | mV | 154 | |||
| Variations between all the different ground pins (including VREF-) | /VSSx-VSS/ | 50 | mV | 154 | |||
| Total current into sum of all VDD power lines (source) | ∑IVDD | 200 | mA | 154 | |||
| Total current out of sum of all VSS ground lines (sink) | ∑IVSS | 200 | mA | 154 | |||
| Maximum current into each VDD power pin (source) | IVDD | 100 | mA | 154 | |||
| Maximum current out of each VSS ground pin (sink) | IVSS | 100 | mA | 154 | |||
| Injected current on FT_xx, TT_xx, RST pins | IINJ(PIN) | -5 | 0 | mA | FT_xx, TT_xx, RST pins | 155 | |
| Storage temperature range | TSTG | -65 | 150 | °C | 155 | ||
| Maximum junction temperature | TJ | 140 | °C | 155 | |||
| Standard operating voltage | VDD | 1.71 | 3.6 | V | IO_VDD_HSLV = 0 | 156 | |
| Standard operating voltage | VDD | 1.71 | 2.7 | V | IO_VDD_HSLV = 1 | 156 | |
| Supply voltage for PG[15:2] I/Os | VDDIO2 | 1.08 | 3.6 | V | At least one I/O in PG[15:2] used, IO_VDDIO2_HSLV = 0 | 156 | |
| Supply voltage for PG[15:2] I/Os | VDDIO2 | 1.08 | 2.7 | V | At least one I/O in PG[15:2] used, IO_VDDIO2_HSLV = 1 | 156 | |
| Supply voltage for PG[15:2] I/Os not used | VDDIO2 | 0 | 3.6 | V | PG[15:2] I/Os not used | 156 | |
| USB supply voltage | VDDUSB | 3 | 3.6 | V | USB used | 156 | |
| USB supply voltage | VDDUSB | 0 | 3.6 | V | USB not used | 156 | |
| Analog supply voltage | VDDA | 1.58 | 3.6 | V | COMP used | 156 | |
| Analog supply voltage | VDDA | 1.6 | 3.6 | V | DAC or OPAMP used | 156 | |
| Analog supply voltage | VDDA | 1.62 | 3.6 | V | ADC used | 156 | |
| Analog supply voltage | VDDA | 1.8 | 3.6 | V | VREFBUF used (normal mode) | 156 | |
| Analog supply voltage | VDDA | 0 | 3.6 | V | ADC, DAC, COMP, OPAMP, and VREFBUF not used | 156 | |
| Backup domain supply voltage | VBAT | 1.65 | 3.6 | V | 156 | ||
| I/O input voltage | VIN | -0.3 | V | All I/Os except FT_c and TT_xx pins; max = Min(min(VDD, VDDA, VDDUSB, VDDIO2)+3.6, 5.5) | 156 | ||
| Input voltage on FT_c I/Os | VIN | -0.3 | 5 | V | FT_c I/Os | 156 | |
| Input voltage on TT_xx I/Os | VIN | -0.3 | V | TT_xx I/Os; max = VDDIOx + 0.3 | 156 | ||
| Sum of output current sourced by all I/Os powered by VSW | IIO_SW | 3 | mA | 156 | |||
| Internal regulator ON, VCORE Range 1 | VCORE | 1.15 | 1.21 | 1.27 | V | Internal regulator ON, Range 1 | 157 |
| Internal regulator ON, VCORE Range 2 | VCORE | 1.05 | 1.1 | 1.15 | V | Internal regulator ON, Range 2 | 157 |
| Internal regulator ON, VCORE Range 3 | VCORE | 0.95 | 1 | 1.05 | V | Internal regulator ON, Range 3 | 157 |
| Internal regulator ON, VCORE Range 4 | VCORE | 0.81 | 0.9 | 0.99 | V | Internal regulator ON, Range 4 | 157 |
| AHB clock frequency | fHCLK | 160 | MHz | Range 1 | 157 | ||
| AHB clock frequency | fHCLK | 110 | MHz | Range 2 | 157 | ||
| AHB clock frequency | fHCLK | 55 | MHz | Range 3 | 157 | ||
| AHB clock frequency | fHCLK | 25 | MHz | Range 4 | 157 | ||
| APB1, APB2, APB3 clock frequency | fPCLKx (x = 1, 2, 3) | 160 | MHz | Range 1 | 157 | ||
| APB1, APB2, APB3 clock frequency | fPCLKx (x = 1, 2, 3) | 110 | MHz | Range 2 | 157 | ||
| APB1, APB2, APB3 clock frequency | fPCLKx (x = 1, 2, 3) | 55 | MHz | Range 3 | 157 | ||
| APB1, APB2, APB3 clock frequency | fPCLKx (x = 1, 2, 3) | 25 | MHz | Range 4 | 157 | ||
| Ambient temperature for suffix 6, maximum power dissipation | TA | -40 | 85 | °C | Maximum power dissipation | 158 | |
| Ambient temperature for suffix 6, low-power dissipation | TA | -40 | 105 | °C | Low-power dissipation | 158 | |
| Junction temperature range, suffix 6 version | TJ | -40 | 105 | °C | Suffix 6 version | 158 | |
| VDD rise-time rate | tVDD | 0 | µs/V | 158 | |||
| VDD fall-time rate | tVDD | 20 | µs/V | ULPMEN = 0 (default value) | 158 | ||
| VDD fall-time rate | tVDD | 250 | ms/V | Standby mode, BOR level 0 selected with ULPMEN = 1 | 158 | ||
| Reset temporization after BOR0 is detected | tRSTTEMPO | 900 | µs | VDD rising | 159 | ||
| Brownout reset threshold 0, rising edge | VBOR0 | 1.6 | 1.66 | 1.71 | V | Rising edge | 159 |
| Brownout reset threshold 0, falling edge | VBOR0 | 1.58 | 1.64 | 1.69 | V | Falling edge, range 1, 2, 3 | 159 |
CAD (KiCad official)
- Symbol:
STM32U575RGT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32u575rgt6-etched.step/stm32u575rgt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32u575rgt6.step/stm32u575rgt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (346 pp, sha256
f3de0b5e62ad45ed, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).