TLC7524EDR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT1	output	Binary-weighted currents are switched between the OUT1 and OUT2 bus lines, maintaining a constant current in each ladder leg.
2	OUT2	output	Binary-weighted currents are switched between the OUT1 and OUT2 bus lines, maintaining a constant current in each ladder leg.
3	GND	power_in	Ground reference pin for the DAC; the datasheet specifies OUT1 and OUT2 at GND for the electrical characteristics.
4	DB7	input	Most significant data input bit (MSB) of the 8-bit digital word latched by the DAC; digital input levels are limited by VIH 2.4V min and VIL 0.8V max at VDD = 5V.
5	DB6	input	Digital data input bit of the 8-bit word; digital input levels are limited by VIH 2.4V min and VIL 0.8V max at VDD = 5V.
6	DB5	input	Digital data input bit of the 8-bit word; digital input levels are limited by VIH 2.4V min and VIL 0.8V max at VDD = 5V.
7	DB4	input	Digital data input bit of the 8-bit word; digital input levels are limited by VIH 2.4V min and VIL 0.8V max at VDD = 5V.
8	DB3	input	Digital data input bit of the 8-bit word; digital input levels are limited by VIH 2.4V min and VIL 0.8V max at VDD = 5V.
9	DB2	input	Digital data input bit of the 8-bit word; digital input levels are limited by VIH 2.4V min and VIL 0.8V max at VDD = 5V.
10	DB1	input	Digital data input bit of the 8-bit word; digital input levels are limited by VIH 2.4V min and VIL 0.8V max at VDD = 5V.
11	DB0	input	Least significant data input bit (LSB) of the 8-bit digital word latched by the DAC; digital input levels are limited by VIH 2.4V min and VIL 0.8V max at VDD = 5V.
12	CS	input	Chip select; when CS is high the data inputs are disabled regardless of the WR state, and CS setup time is 40 ns min.
13	WR	input	Write control; when CS and WR are both low the input latches are transparent, and WR pulse duration low is 40 ns min.
14	VDD	power_in	Supply voltage pin; the device operates from a 5V to 15V single supply, with VDD = 5V range 4.75V to 5.25V.
15	REF	input	Reference voltage input, Vref, specified at ±10V; the reference input impedance (REF to GND) is 5 kΩ min to 20 kΩ typ.
16	RFB	passive	Feedback resistor connection for the internal R-2R ladder amplifier feedback, used with an external operational amplifier.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Data Acquisition
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VDD	4.75	5	5.25	V	VDD = 5V	3
Supply voltage	VDD	14.5	15	15.5	V	VDD = 15V	3
Low-level input voltage	VIL			0.8	V	VDD = 5V	3
Low-level input voltage	VIL			1.5	V	VDD = 15V	3
High-level input voltage	VIH	2.4			V	VDD = 5V	3
High-level input voltage	VIH	13.5			V	VDD = 15V	3
CS setup time	tsu(CS)	40			ns	VDD = 5V	3
CS hold time	th(CS)	0			ns	VDD = 5V	3
Data bus input setup time	tsu(D)	25			ns	VDD = 5V	3
Data bus input hold time	th(D)	10			ns	VDD = 5V	3
Pulse duration, WR low	tw(WR)	40			ns	VDD = 5V	3
Operating free-air temperature, TLC7524E	TA	-40		85	°C	TLC7524E grade	3
Supply voltage range	VDD	-0.3		16.5	V		2
Digital input voltage range	VI	-0.3			V	upper limit VDD + 0.3V	2
Reference voltage	Vref	-25		25	V		2
Peak digital input current	II			10	µA		2
Operating free-air temperature range, TLC7524E	TA	-40		85	°C	TLC7524E grade	2
Storage temperature range	Tstg	-65		150	°C		2
Lead temperature 1.6 mm from case, 10 s, D package				260	°C	D, N, or PW package, 10 seconds	2
IIH High-level input current	IIH			10	µA	VI = VDD	3
IIL Low-level input current	IIL	-10			µA	VI = 0	3
Output leakage current OUT1	IIkg	-400		400	nA	VDD = 5V; OUT1 DB0−DB7 at 0V, Vref = ±10V, WR, CS at 0V	3
Output leakage current OUT1	IIkg	-200		200	nA	VDD = 15V; OUT1 DB0−DB7 at 0V, Vref = ±10V, WR, CS at 0V	3
Output leakage current OUT2	IIkg	-400		400	nA	VDD = 5V; OUT2 DB0−DB7 at VDD, Vref = ±10V, WR, CS at 0V	3
Output leakage current OUT2	IIkg	-200		200	nA	VDD = 15V; OUT2 DB0−DB7 at VDD, Vref = ±10V, WR, CS at 0V	3
Supply current quiescent	IDD		1	2	mA	DB0−DB7 at VIHmin or VILmax	3
Supply current standby	IDD			500	µA	DB0−DB7 at 0V or VDD	3
Supply voltage sensitivity, ∆gain/∆VDD	kSVS		0.01	0.16	%FSR/%	VDD = 5V; ∆VDD = ±10%	3
Supply voltage sensitivity, ∆gain/∆VDD	kSVS		0.005	0.04	%FSR/%	VDD = 15V; ∆VDD = ±10%	3
Input capacitance DB0−DB7, WR, CS	Ci			5	pF	VI = 0	3
Output capacitance OUT1	Co			30	pF	DB0−DB7 at 0V, WR, CS at 0V	3
Output capacitance OUT2	Co			120	pF	DB0−DB7 at 0V, WR, CS at 0V	3
Output capacitance OUT1	Co			120	pF	DB0−DB7 at VDD, WR, CS at 0V	3
Output capacitance OUT2	Co			30	pF	DB0−DB7 at VDD, WR, CS at 0V	3
Reference input impedance (REF to GND)		5		20	kΩ	REF to GND	3
Linearity error		-0.5		0.5	LSB		4
Gain error		-2.5		2.5	LSB	See Note 1	4
Settling time (to 1/2 LSB)				100	ns	See Note 2	4
Propagation delay from digital input to 90% of final analog output current				80	ns	See Note 2	4
Feedthrough at OUT1 or OUT2				0.5	%FSR	Vref = ±10V (100kHz sinewave); WR and CS at 0V, DB0−DB7 at 0V	4
Temperature coefficient of gain		-0.004		0.004	%FSR/°C	VDD = 5V; TA = +25°C to MAX	4
Temperature coefficient of gain		-0.001		0.001	%FSR/°C	VDD = 15V; TA = +25°C to MAX	4
Linearity error at REF				1	LSB	VDD = 5V, OUT1 = 2.5V, OUT2 at GND, TA = +25°C	5

CAD (KiCad official)

Symbol: TLC7524EDR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: tlc7524edr-etched.step / tlc7524edr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc7524edr.step / tlc7524edr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (28 pp, sha256 ce7ba0309086b44c, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TLC7524EDR

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3D Model

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