ADUM7441ARQZ from Analog Devices, in a QSOP-16-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1A	power_in	Supply voltage A for isolator side 1, 3.0 V to 5.5 V; pin 1 must be connected externally to pin 7, with a 0.01 µF to 0.1 µF ceramic bypass capacitor between VDD1A and GND1 (pin 2).
2	GND1	power_in	Ground reference for isolator side 1; pins 2 and 8 are internally connected and connecting both to GND1 is recommended.
3	VIA	input	Logic input A; the absolute maximum input voltage range is −0.5 V to VDDI + 0.5 V.
4	VIB	input	Logic input B; the absolute maximum input voltage range is −0.5 V to VDDI + 0.5 V.
5	VIC	input	Logic input C; the absolute maximum input voltage range is −0.5 V to VDDI + 0.5 V.
6	VOD	output	Logic output D; the absolute maximum output voltage range is −0.5 V to VDDO + 0.5 V, and average output current per pin is limited to −10 mA to +10 mA.
7	VDD1B	power_in	Supply voltage B for isolator side 1, 3.0 V to 5.5 V; pin 7 must be connected externally to pin 1, with a 0.01 µF to 0.1 µF ceramic bypass capacitor between VDD1B and GND1 (pin 8).
8	GND1	power_in	Ground reference for isolator side 1; pins 2 and 8 are internally connected and connecting both to GND1 is recommended.
9	GND2	power_in	Ground reference for isolator side 2; pins 9 and 15 are internally connected and connecting both to GND2 is recommended.
10	VDD2B	power_in	Supply voltage B for isolator side 2, 3.0 V to 5.5 V; pin 10 must be connected externally to pin 16, with a 0.01 µF to 0.1 µF ceramic bypass capacitor between VDD2B and GND2 (pin 9).
11	VID	input	Logic input D; the absolute maximum input voltage range is −0.5 V to VDDI + 0.5 V.
12	VOC	output	Logic output C; the absolute maximum output voltage range is −0.5 V to VDDO + 0.5 V, and average output current per pin is limited to −10 mA to +10 mA.
13	VOB	output	Logic output B; the absolute maximum output voltage range is −0.5 V to VDDO + 0.5 V, and average output current per pin is limited to −10 mA to +10 mA.
14	VOA	output	Logic output A; the absolute maximum output voltage range is −0.5 V to VDDO + 0.5 V, and average output current per pin is limited to −10 mA to +10 mA.
15	GND2	power_in	Ground reference for isolator side 2; pins 9 and 15 are internally connected and connecting both to GND2 is recommended.
16	VDD2A	power_in	Supply voltage A for isolator side 2, 3.0 V to 5.5 V; pin 16 must be connected externally to pin 10, with a 0.01 µF to 0.1 µF ceramic bypass capacitor between VDD2A and GND2 (pin 15).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	QSOP-16-150mil
Category	Interface ICs
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage Temperature (TST) Range	TST	-65		150	°C		10
Ambient Operating Temperature (TA)	TA	-40		105	°C		10
Supply Voltages	VDD1, VDD2	-0.5		7	V		10
Input Voltages	VIA, VIB, VIC, VID	-0.5			V		10
Output Voltages	VOA, VOB, VOC, VOD	-0.5			V		10
Average Output Current per Pin, Side 1	IO1	-10		10	mA		10
Average Output Current per Pin, Side 2	IO2	-10		10	mA		10
Common-Mode Transients		-100		100	kV/µs		10
Operating Temperature	TA	-40		105	°C		9
Supply Voltages	VDD1, VDD2	3		5.5	V		9
Propagation Delay (A grade, 5 V operation)	tPHL, tPLH		50	75	ns	50% input to 50% output	4
Pulse Width Distortion (A grade, 5 V operation)	PWD		10	25	ns	/tPLH − tPHL/	4
Pulse Width (A grade, 5 V operation)	PW	250			ns	Within PWD limit	4
Propagation Delay Skew (A grade, 5 V operation)	tPSK			20	ns		4
Codirectional Channel Matching (A grade, 5 V operation)	tPSKCD			25	ns		4
Opposing-Direction Channel Matching (A grade, 5 V operation)	tPSKOD			30	ns		4
Supply Current ADuM7441 side 1, 1 Mbps (A grade, 5 V operation)	IDD1		4.1	4.9	mA		4
Supply Current ADuM7441 side 2, 1 Mbps (A grade, 5 V operation)	IDD2		3.6	4.7	mA		4
Quiescent Input Supply Current (5 V operation)	IDDI(Q)		0.76	0.95	mA		4
Quiescent Output Supply Current (5 V operation)	IDDO(Q)		0.57	0.73	mA		4
Input Current per Channel (5 V operation)	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx	4
Logic Low Output Voltage (5 V operation)	VOL		0	0.1	V	IOx = 20 µA, VIx = VIxL	4
Logic Low Output Voltage (5 V operation)	VOL		0.2	0.4	V	IOx = 4 mA, VIx = VIxL	4
Common-Mode Transient Immunity (5 V operation)	/CM/	15	25		kV/µs	VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V	5
Propagation Delay (A grade, 3.3 V operation)	tPHL, tPLH		60	85	ns	50% input to 50% output	5
Pulse Width Distortion (A grade, 3.3 V operation)	PWD		10	25	ns	/tPLH − tPHL/	5
Pulse Width (A grade, 3.3 V operation)	PW	250			ns	Within PWD limit	5
Propagation Delay Skew (A grade, 3.3 V operation)	tPSK			20	ns		5
Codirectional Channel Matching (A grade, 3.3 V operation)	tPSKCD			25	ns		5
Opposing-Direction Channel Matching (A grade, 3.3 V operation)	tPSKOD			30	ns		5
Supply Current ADuM7441 side 1, 1 Mbps (A grade, 3.3 V operation)	IDD1		2.8	3.5	mA		5
Supply Current ADuM7441 side 2, 1 Mbps (A grade, 3.3 V operation)	IDD2		2.5	3.3	mA		5
Input Current per Channel (3.3 V operation)	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx	6
Logic Low Output Voltage (3.3 V operation)	VOL		0	0.1	V	IOx = 20 µA, VIx = VIxL	6
Logic Low Output Voltage (3.3 V operation)	VOL		0.2	0.4	V	IOx = 4 mA, VIx = VIxL	6
Common-Mode Transient Immunity (3.3 V operation)	/CM/	15	20		kV/µs	VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V	6
Propagation Delay (A grade, 5 V/3.3 V mixed operation)	tPHL, tPLH		55	80	ns	50% input to 50% output	6
Pulse Width Distortion (A grade, 5 V/3.3 V mixed operation)	PWD		10	25	ns	/tPLH − tPHL/	6
Pulse Width (A grade, 5 V/3.3 V mixed operation)	PW	250			ns	Within PWD limit	6
Propagation Delay Skew (A grade, 5 V/3.3 V mixed operation)	tPSK			20	ns		6
Codirectional Channel Matching (A grade, 5 V/3.3 V mixed operation)	tPSKCD			25	ns		6
Opposing-Direction Channel Matching (A grade, 5 V/3.3 V mixed operation)	tPSKOD			30	ns		6
Supply Current ADuM7441 side 1, 1 Mbps (A grade, 5 V/3.3 V mixed operation)	IDD1		3.7	5	mA		6
Supply Current ADuM7441 side 2, 1 Mbps (A grade, 5 V/3.3 V mixed operation)	IDD2		2.2	2.8	mA		6
Input Current per Channel (5 V/3.3 V mixed operation)	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx	7
Logic Low Output Voltage (5 V/3.3 V mixed operation)	VOL		0	0.1	V	IOx = 20 µA, VIx = VIxL	7
Logic Low Output Voltage (5 V/3.3 V mixed operation)	VOL		0.2	0.4	V	IOx = 4 mA, VIx = VIxL	7
Propagation Delay (A grade, 3.3 V/5 V mixed operation)	tPHL, tPLH		55	80	ns	50% input to 50% output	7
Pulse Width Distortion (A grade, 3.3 V/5 V mixed operation)	PWD		10	25	ns	/tPLH − tPHL/	7
Pulse Width (A grade, 3.3 V/5 V mixed operation)	PW	250			ns	Within PWD limit	7
Propagation Delay Skew (A grade, 3.3 V/5 V mixed operation)	tPSK			20	ns		7
Codirectional Channel Matching (A grade, 3.3 V/5 V mixed operation)	tPSKCD			25	ns		7
Opposing-Direction Channel Matching (A grade, 3.3 V/5 V mixed operation)	tPSKOD			30	ns		7
Supply Current ADuM7441 side 1, 1 Mbps (A grade, 3.3 V/5 V mixed operation)	IDD1		2.5	3.3	mA		8
Supply Current ADuM7441 side 2, 1 Mbps (A grade, 3.3 V/5 V mixed operation)	IDD2		3.6	4.6	mA		8
Input Current per Channel (3.3 V/5 V mixed operation)	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx	8
Logic Low Output Voltage (3.3 V/5 V mixed operation)	VOL		0	0.1	V	IOx = 20 µA, VIx = VIxL	8
Logic Low Output Voltage (3.3 V/5 V mixed operation)	VOL		0.2	0.4	V	IOx = 4 mA, VIx = VIxL	8
Common-Mode Transient Immunity (3.3 V/5 V mixed operation)	/CM/	15	20		kV/µs	VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V	8
IC Junction-to-Ambient Thermal Resistance	θJA		76		°C/W	Thermocouple located at center of package underside	8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	abs		3 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up	10

CAD (KiCad official)

Symbol: ADUM7441ARQZ
Footprint: Package_SO:QSOP-16_3.9x4.9mm_P0.635mm
3D model: QSOP-16-150mil (KiCad packages3D, STEP)
3D model files: adum7441arqz-etched.step / adum7441arqz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum7441arqz.step / adum7441arqz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (20 pp, sha256 1941e7b1b019a8b5, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADUM7441ARQZ

Verified ADUM7441ARQZ

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3D Model

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