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74LVC74AD

Public Made by Adom

by adom

Nexperia Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74LVC74AD

Nexperia · Flip Flops · SOIC-14

74LVC74AD from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1RD input Asynchronous reset-direct input (active LOW); when LOW it forces 1Q LOW and 1Q HIGH independent of the clock.
2 1D input Data input; its level is transferred to 1Q on the LOW-to-HIGH transition of 1CP and must be stable one set-up time before that transition.
3 1CP input Clock input, edge-triggered on the LOW-to-HIGH transition, with Schmitt trigger action.
4 1SD input Asynchronous set-direct input (active LOW); when LOW it forces 1Q HIGH and 1Q LOW independent of the clock.
5 1Q output True output of flip-flop 1.
6 1Q output Complement output of flip-flop 1.
7 GND power_in Ground (0 V) reference for all voltages.
8 2Q output Complement output of flip-flop 2.
9 2Q output True output of flip-flop 2.
10 2SD input Asynchronous set-direct input (active LOW); when LOW it forces 2Q HIGH and 2Q LOW independent of the clock.
11 2CP input Clock input, edge-triggered on the LOW-to-HIGH transition, with Schmitt trigger action.
12 2D input Data input; its level is transferred to 2Q on the LOW-to-HIGH transition of 2CP and must be stable one set-up time before that transition.
13 2RD input Asynchronous reset-direct input (active LOW); when LOW it forces 2Q LOW and 2Q HIGH independent of the clock.
14 VCC power_in Supply voltage; recommended operating range is 1.2 V to 3.6 V (Table 6).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 6.5 V 4
input clamping current IIK -50 mA VI < 0 V 4
input voltage VI -0.5 6.5 V 4
output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 4
output voltage VO -0.5 V 4
output current IO -50 50 mA VO = 0 V to VCC 4
supply current ICC 100 mA 4
ground current IGND -100 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
supply voltage for maximum speed performance VCC 1.65 3.6 V for maximum speed performance 5
supply voltage for low-voltage applications VCC 1.2 3.6 V for low-voltage applications 5
input voltage VI 0 5.5 V 5
output voltage VO 0 V 5
ambient temperature Tamb -40 125 °C 5
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 5
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 5
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 5
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 5
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 5
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 5
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 5
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 5
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V 5
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V 5
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V 5
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V 5
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V 5
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V 5
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V 5
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V 5
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V 5
input leakage current II -20 20 μA VCC = 3.6 V; VI = 5.5 V or GND 5
supply current ICC 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 5
additional supply current ΔICC 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 6
propagation delay nCP to nQ, nQ tpd 1 5 11.9 ns VCC = 1.65 V to 1.95 V; see Fig. 7 6
propagation delay nCP to nQ, nQ tpd 1.8 2.9 6.7 ns VCC = 2.3 V to 2.7 V; see Fig. 7 6
propagation delay nCP to nQ, nQ tpd 1 2.7 7.5 ns VCC = 2.7 V; see Fig. 7 6
propagation delay nCP to nQ, nQ tpd 1 2.6 6.5 ns VCC = 3.0 V to 3.6 V; see Fig. 7 6
clock pulse width HIGH or LOW tW 5 ns VCC = 1.65 V to 1.95 V; see Fig. 7 6
clock pulse width HIGH or LOW tW 4 ns VCC = 2.3 V to 2.7 V; see Fig. 7 6
clock pulse width HIGH or LOW tW 4.5 ns VCC = 2.7 V; see Fig. 7 6
clock pulse width HIGH or LOW tW 4.5 1.3 ns VCC = 3.0 V to 3.6 V; see Fig. 7 6
recovery time trec 1.5 ns set or reset LOW; VCC = 1.65 V to 1.95 V; see Fig. 8 7
recovery time trec 1 ns set or reset LOW; VCC = 2.7 V; see Fig. 8 7
recovery time trec 1 -3 ns set or reset LOW; VCC = 3.0 V to 3.6 V; see Fig. 8 7
set-up time nD to nCP tsu 3 ns VCC = 1.65 V to 1.95 V; see Fig. 7 7
set-up time nD to nCP tsu 2.5 ns VCC = 2.3 V to 2.7 V; see Fig. 7 7
set-up time nD to nCP tsu 2.2 ns VCC = 2.7 V; see Fig. 7 7
set-up time nD to nCP tsu 2 0.8 ns VCC = 3.0 V to 3.6 V; see Fig. 7 7
hold time nCP to nD th 2 ns VCC = 1.65 V to 1.95 V; see Fig. 7 7
hold time nCP to nD th 1.5 ns VCC = 2.3 V to 2.7 V; see Fig. 7 7
hold time nCP to nD th 1 ns VCC = 2.7 V; see Fig. 7 7
hold time nCP to nD th 1 -0.2 ns VCC = 3.0 V to 3.6 V; see Fig. 7 7
maximum frequency nCP fmax 80 MHz VCC = 1.65 V to 1.95 V; see Fig. 7 7
maximum frequency nCP fmax 100 MHz VCC = 2.3 V to 2.7 V; see Fig. 7 7
maximum frequency nCP fmax 120 MHz VCC = 2.7 V; see Fig. 7 7
maximum frequency nCP fmax 120 250 MHz VCC = 3.0 V to 3.6 V; see Fig. 7 7

CAD (KiCad official)

  • Symbol: 74LVC74AD
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: 74lvc74ad-etched.step / 74lvc74ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc74ad.step / 74lvc74ad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 66c1f80f9550c368, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF