component
UCC28060DR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC28060DR
Texas Instruments · AC-DC Controllers And Regulators · SOIC-16
UCC28060DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ZCDB | input | Zero current detection input for phase B: expects negative edge when phase B inductor current decays to zero, clamped at 0V to 3V, requires series resistor limiting clamping current to less than ±3mA. |
| 2 | VSENSE | input | Output DC voltage sense: connect to voltage divider across power converter output with 6V error amplifier reference, can be pulled low by open-drain logic to disable gate drivers and reduce VCC current. |
| 3 | TSET | input | Timing set: PWM on-time programming input to set on-time versus COMP voltage and minimum period at gate drive outputs, connect resistor from TSET to AGND. |
| 4 | PHB | input | Phase B enable: turns on/off channel B of boost converter with thresholds changing with line range, can be driven by external logic signals for customized phase management or connected to VREF to disable phase management. |
| 5 | COMP | output | Error amplifier output: high-impedance current source for voltage regulation loop compensation components to AGND, on-time proportional to voltage at pin minus 125mV offset, pulled low during soft-start events. |
| 6 | AGND | power_in | Analog ground: connect analog signal bypass capacitors, compensation components, and analog signal returns to this pin, connect analog and power grounds at single point to isolate high-current noise from low-current analog circuits. |
| 7 | VINAC | input | Input AC voltage sense: connect to voltage divider across rectified input power mains to sense input voltage range and brownout, input voltage range changes when peak voltage becomes and stays below or above range change threshold. |
| 8 | HVSEN | input | High voltage output sense: FailSafe OVP monitors output over-voltage with redundant protection through VSENSE and HVSEN pins, can enable downstream power converter, must never fall below 0.8V during normal operation. |
| 9 | PWMCNTL | output | PWM enable logic output: open-drain output goes low when HVSEN within good region and ZCDA and ZCDB inputs switching correctly in two-phase mode, otherwise high impedance. |
| 10 | CS | input | Current sense input: connect current sense resistor and negative diode bridge terminal, cycle-by-cycle over-current protection limits input current by turning off both gate drivers when CS more negative than rising threshold of approximately -200mV. |
| 11 | GDB | output | Channel B gate drive output: connect to power FET gate for phase B through shortest connection practical, add 5Ω to 10Ω series resistor if trace longer than 0.5 inches to reduce ringing from trace inductance. |
| 12 | VCC | power_in | Bias supply input: connect to controlled bias supply of 14V to 21V with 0.1µF ceramic bypass capacitor to PGND, supply must deliver 6mA DC plus transient MOSFET gate charging current. |
| 13 | PGND | power_in | Power ground for integrated circuit: connect this pin to AGND through separate short trace to isolate gate driver noise from analog signals. |
| 14 | GDA | output | Channel A gate drive output: connect to power FET gate for phase A through shortest connection practical, add 5Ω to 10Ω series resistor if trace longer than 0.5 inches to reduce ringing from trace inductance. |
| 15 | VREF | power_in | Voltage reference output: provides 6VDC reference for biasing other circuits requiring less than 2mA of total supply current, connect 0.1µF ceramic bypass capacitor from pin to AGND. |
| 16 | ZCDA | input | Zero current detection input for phase A: expects negative edge when phase A inductor current decays to zero, clamped at 0V to 3V, requires series resistor limiting clamping current to less than ±3mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
UCC28060DR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
ucc28060dr-etched.step/ucc28060dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28060dr.step/ucc28060dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
7003bef7749e1a21, retrieved 2026-10-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).