component
CA-IS3763HN
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCA-IS3763HN
Chipanalog · Digital Isolators · SOIC-16
CA-IS3763HN from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | A-side supply voltage, recommended 2.375 V to 5.5 V, to be decoupled with a 0.1 µF to 1 µF bypass capacitor placed within 2 mm of the pin. |
| 2 | VI1 | input | A-side logic input for forward channel 1, TTL-compatible with a Schmitt-trigger input (VIH min 2.0 V, VIL max 0.8 V). |
| 3 | VI2 | input | A-side logic input for forward channel 2, TTL-compatible with a Schmitt-trigger input (VIH min 2.0 V, VIL max 0.8 V). |
| 4 | VI3 | input | A-side logic input for forward channel 3, TTL-compatible with a Schmitt-trigger input (VIH min 2.0 V, VIL max 0.8 V). |
| 5 | VO4 | output | A-side logic output of reverse channel 4 on the CA-IS3763, rail-to-rail with about 50 Ω output impedance. |
| 6 | VO5 | output | A-side logic output of reverse channel 5 on the CA-IS3763, rail-to-rail with about 50 Ω output impedance. |
| 7 | VO6 | output | A-side logic output of reverse channel 6 on the CA-IS3763, rail-to-rail with about 50 Ω output impedance. |
| 8 | GNDA | power_in | A-side ground reference point for the isolator's A-side circuitry and signals. |
| 9 | GNDB | power_in | B-side ground reference point, isolated from GNDA by the isolation barrier. |
| 10 | VI6 | input | B-side logic input for reverse channel 6 on the CA-IS3763, TTL-compatible with a Schmitt-trigger input (VIH min 2.0 V, VIL max 0.8 V). |
| 11 | VI5 | input | B-side logic input for reverse channel 5 on the CA-IS3763, TTL-compatible with a Schmitt-trigger input (VIH min 2.0 V, VIL max 0.8 V). |
| 12 | VI4 | input | B-side logic input for reverse channel 4 on the CA-IS3763, TTL-compatible with a Schmitt-trigger input (VIH min 2.0 V, VIL max 0.8 V). |
| 13 | VO3 | output | B-side logic output of forward channel 3, rail-to-rail with about 50 Ω output impedance. |
| 14 | VO2 | output | B-side logic output of forward channel 2, rail-to-rail with about 50 Ω output impedance. |
| 15 | VO1 | output | B-side logic output of forward channel 1, rail-to-rail with about 50 Ω output impedance. |
| 16 | VDDB | power_in | B-side supply voltage, recommended 2.375 V to 5.5 V, to be decoupled with a 0.1 µF to 1 µF bypass capacitor placed within 2 mm of the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Absolute max supply voltage VDDA, VDDB | VDDA, VDDB | -0.5 | 7 | V | Voltages relative to local ground (GNDA or GNDB), peak | 5 | |
| Absolute max input voltage Ax, Bx | Vin | -0.5 | V | 5 | |||
| Absolute max output current | IO | -20 | 20 | mA | 5 | ||
| Absolute max junction temperature | TJ | 150 | °C | 5 | |||
| Absolute max storage temperature | TSTG | -65 | 150 | °C | 5 | ||
| Recommended supply voltage VDDA, VDDB | VDDA, VDDB | 2.375 | 3.3 | 5.5 | V | 5 | |
| UVLO threshold, VDD rising | VDD(UVLO+) | 1.95 | 2.24 | 2.375 | V | 5 | |
| UVLO threshold, VDD falling | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | 5 | |
| UVLO hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | 5 | |
| High-level output current IOH | IOH | -4 | mA | VDDO = 5 V | 5 | ||
| Low-level output current IOL | IOL | 4 | mA | VDDO = 5 V | 5 | ||
| Input threshold logic high (recommended) | VIH | 2 | V | 5 | |||
| Input threshold logic low (recommended) | VIL | 0.8 | V | 5 | |||
| Signal data rate | DR | 0 | 150 | Mbps | 5 | ||
| Ambient temperature | TA | -40 | 27 | 125 | °C | 5 | |
| Output logic low voltage | VOL | 0.2 | 0.4 | V | VDDA = VDDB = 5 V ±10%, TA = -40 to 125°C; IOL = 4mA; Fig 8-1 | 9 | |
| Input threshold logic high VIT+(IN) | VIT+(IN) | 2 | V | VDDA = VDDB = 5 V ±10%, TA = -40 to 125°C | 9 | ||
| Input threshold logic low VIT-(IN) | VIT-(IN) | 0.8 | V | VDDA = VDDB = 5 V ±10%, TA = -40 to 125°C | 9 | ||
| Input high-level leakage current | IIH | 20 | µA | VIH = VDDA at Ax or Bx; VDDA = VDDB = 5 V ±10% | 9 | ||
| Input low-level leakage current | IIL | -20 | µA | VIL = 0 V at Ax or Bx; VDDA = VDDB = 5 V ±10% | 9 | ||
| Common-mode transient immunity CMTI | CMTI | 100 | 150 | kV/µs | VI = VDDI 1 or 0 V, VCM = 1200 V; Fig 8-3; VDDA = VDDB = 5 V ±10% | 9 | |
| Output impedance tolerance | ZO | -40 | 40 | % | Normal isolator channel output impedance ~50 Ω ±40% (note 2) | 9 | |
| Supply current IDDA, DC, VIN = VDDI (H variant) | IDDA | 3.2 | 5.1 | mA | DC signal; VIN = VDDI (CA-IS3763H); VDDA = VDDB = 5 V ±10% | 10 | |
| Supply current IDDB, DC, VIN = VDDI (H variant) | IDDB | 3.2 | 5.1 | mA | DC signal; VIN = VDDI (CA-IS3763H); VDDA = VDDB = 5 V ±10% | 10 | |
| Supply current IDDA, DC, VIN = 0 V (H variant) | IDDA | 7.1 | 11.4 | mA | DC signal; VIN = 0V (CA-IS3763H); VDDA = VDDB = 5 V ±10% | 10 | |
| Supply current IDDB, DC, VIN = 0 V (H variant) | IDDB | 7.1 | 11.4 | mA | DC signal; VIN = 0V (CA-IS3763H); VDDA = VDDB = 5 V ±10% | 10 | |
| Supply current IDDA, AC 1 Mbps | IDDA | 5.4 | 8.6 | mA | AC: 1Mbps (500kHz); all channels 50% duty square wave 5 V; CL = 15 pF | 10 | |
| Supply current IDDB, AC 1 Mbps | IDDB | 5.4 | 8.6 | mA | AC: 1Mbps (500kHz); all channels 50% duty square wave 5 V; CL = 15 pF | 10 | |
| Supply current IDDA, AC 10 Mbps | IDDA | 7.4 | 11.6 | mA | AC: 10Mbps (5MHz); all channels 50% duty square wave 5 V; CL = 15 pF | 10 | |
| Supply current IDDB, AC 10 Mbps | IDDB | 7.4 | 11.6 | mA | AC: 10Mbps (5MHz); all channels 50% duty square wave 5 V; CL = 15 pF | 10 | |
| Supply current IDDA, AC 100 Mbps | IDDA | 27.7 | 42.2 | mA | AC: 100Mbps (50MHz); all channels 50% duty square wave 5 V; CL = 15 pF | 10 | |
| Supply current IDDB, AC 100 Mbps | IDDB | 27.7 | 42.2 | mA | AC: 100Mbps (50MHz); all channels 50% duty square wave 5 V; CL = 15 pF | 10 | |
| Data rate DR | DR | 0 | 150 | Mbps | VDDA = VDDB = 5 V ±10% | 13 | |
| Minimum pulse width PWmin | PWmin | 5 | ns | VDDA = VDDB = 5 V ±10% | 13 | ||
| Propagation delay tPLH, tPHL | tPLH, tPHL | 5 | 12 | 15 | ns | Fig 8-1; VDDA = VDDB = 5 V ±10% | 13 |
| Pulse width distortion PWD | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/; VDDA = VDDB = 5 V ±10% | 13 | |
| Channel-to-channel output skew tsk(o) | tsk(o) | 0.4 | 2.5 | ns | Same-direction channels (note 1); VDDA = VDDB = 5 V ±10% | 13 | |
| Part-to-part output skew tsk(pp) | tsk(pp) | 2 | 4.5 | ns | Part-to-part, same direction (note 2); VDDA = VDDB = 5 V ±10% | 13 | |
| Output rise time tr | tr | 2.5 | 4 | ns | Fig 8-1; VDDA = VDDB = 5 V ±10% | 13 | |
| Output fall time tf | tf | 2.5 | 4 | ns | Fig 8-1; VDDA = VDDB = 5 V ±10% | 13 | |
| Default output delay time from input power loss tDO | tDO | 8 | 12 | µs | Fig 8-2; VDDA = VDDB = 5 V ±10% | 13 | |
| Startup time tSU | tSU | 15 | 40 | µs | VDDA = VDDB = 5 V ±10% | 13 | |
| Output logic high voltage VOH | VOH | 4.8 | V | IOH = -4mA; Fig 8-1; VDDA = VDDB = 5 V ±10% | 9 | ||
| Output impedance ZO | ZO | 50 | Ω | Normal isolator channel (note 2) | 9 | ||
| Input capacitance CI | CI | 2 | pF | VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V; measured pin to ground | 9 | ||
| Thermal resistance junction-to-ambient RθJA (SOIC16-NB, N) | RθJA | 96.2 | °C/W | SOIC16-NB(N) package | 6 |
CAD (KiCad official)
- Symbol:
CA-IS3763HN - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
ca-is3763hn-etched.step/ca-is3763hn-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3763hn.step/ca-is3763hn.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (23 pp, sha256
5297fd5a42777b27, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).