component
CDCVF25081PW
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCDCVF25081PW
Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-16
CDCVF25081PW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLKIN | input | Clock input that must have a fixed frequency and phase for the PLL to acquire lock, and a stabilization time is required after power-up and valid signal application. |
| 2 | 1Y0 | output | Bank 1 Y0 clock output with an integrated 25-Ω series-damping resistor. |
| 3 | 1Y1 | output | Bank 1 Y1 clock output with an integrated 25-Ω series-damping resistor. |
| 4 | VDD | power_in | 3.3 V power supply for the output channels and core voltage (3 V to 3.6 V supply range per recommended operating conditions). |
| 5 | GND | power_in | Ground; connect to system ground. |
| 6 | 2Y0 | output | Bank 2 Y0 clock output with an integrated 25-Ω series-damping resistor. |
| 7 | 2Y1 | output | Bank 2 Y1 clock output with an integrated 25-Ω series-damping resistor. |
| 8 | S2 | input | Input selection pin that, together with S1, selects the input port and output source (PLL, bypassed PLL, or high-impedance) per Table 8-2. |
| 9 | S1 | input | Input selection pin that, together with S2, selects the input port and output source (PLL, bypassed PLL, or high-impedance) per Table 8-2. |
| 10 | 2Y2 | output | Bank 2 Y2 clock output with an integrated 25-Ω series-damping resistor. |
| 11 | 2Y3 | output | Bank 2 Y3 clock output with an integrated 25-Ω series-damping resistor. |
| 12 | GND | power_in | Ground; connect to system ground. |
| 13 | VDD | power_in | 3.3 V power supply for the output channels and core voltage (3 V to 3.6 V supply range per recommended operating conditions). |
| 14 | 1Y2 | output | Bank 1 Y2 clock output with an integrated 25-Ω series-damping resistor. |
| 15 | 1Y3 | output | Bank 1 Y3 clock output with an integrated 25-Ω series-damping resistor. |
| 16 | FBIN | input | Feedback input to the internal PLL that must be wired to one of the outputs to complete the feedback loop for zero-delay operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Clock/Timing |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CDCVF25081PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cdcvf25081pw-etched.step/cdcvf25081pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdcvf25081pw.step/cdcvf25081pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
9f846462bdac0c0a, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).