component
LMK05318RGZT
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-48-EP(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownLMK05318RGZT
Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · VQFN-48-EP(7x7)
LMK05318RGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STATUS0 | output | Programmable status output 0; configurable for device status and interrupt signals |
| 2 | STATUS1/FDEC | bidirectional | Status output 1 or DPLL DCO frequency decrement input in I2C mode |
| 3 | CAP_DIG | passive | External bypass capacitor for digital core LDO; recommend 10µF |
| 4 | VDD_DIG | power_in | 3.3V core power supply for digital block; bypass with 1µF capacitor |
| 5 | VDD_IN | power_in | 3.3V core power supply for PRIREF and SECREF inputs; bypass with 10µF capacitor |
| 6 | PRIREF_P | input | Primary reference clock differential input positive terminal, 5MHz to 800MHz |
| 7 | PRIREF_N | input | Primary reference clock differential input negative terminal, 5MHz to 800MHz |
| 8 | REFSEL | input | Manual DPLL reference input selection (3-level, 1.8V compatible); 0=PRIREF, 1=SECREF, floating=auto |
| 9 | HW_SW_CTRL | input | Device startup mode selection (3-level, 1.8V compatible); sampled during power-on reset |
| 10 | SECREF_P | input | Secondary reference clock differential input positive terminal, 5MHz to 800MHz |
| 11 | SECREF_N | input | Secondary reference clock differential input negative terminal, 5MHz to 800MHz |
| 12 | GPIO0/SYNCN | bidirectional | Output synchronization active-low input or programmable GPIO output |
| 13 | PDN | input | Device power down active-low input; pulling low disables all device blocks and serial interface |
| 14 | OUT0_P | output | Clock output 0 positive; AC-LVDS/CML/LVPECL/HCSL format, 2MHz to 800MHz |
| 15 | OUT0_N | output | Clock output 0 negative; AC-LVDS/CML/LVPECL/HCSL format, 2MHz to 800MHz |
| 16 | OUT1_N | output | Clock output 1 negative; AC-LVDS/CML/LVPECL/HCSL format, 2MHz to 800MHz |
| 17 | OUT1_P | output | Clock output 1 positive; AC-LVDS/CML/LVPECL/HCSL format, 2MHz to 800MHz |
| 18 | VDDO_01 | power_in | Output power supply for OUT0-OUT3 (1.8V/2.5V/3.3V); bypass with 0.1µF capacitor |
| 19 | VDDO_23 | power_in | Output power supply for OUT0-OUT3 (1.8V/2.5V/3.3V); bypass with 0.1µF capacitor |
| 20 | OUT2_P | output | Clock output 2 positive; AC-LVDS/CML/LVPECL/HCSL format, 2MHz to 800MHz |
| 21 | OUT2_N | output | Clock output 2 negative; AC-LVDS/CML/LVPECL/HCSL format, 2MHz to 800MHz |
| 22 | OUT3_N | output | Clock output 3 negative; AC-LVDS/CML/LVPECL/HCSL format, 2MHz to 800MHz |
| 23 | OUT3_P | output | Clock output 3 positive; AC-LVDS/CML/LVPECL/HCSL format, 2MHz to 800MHz |
| 24 | GPIO1/SCS | input | I2C address LSB select (3-level) sampled on power-on reset or SPI chip select in SPI mode |
| 25 | SDA/SDI | bidirectional | I2C serial data open-drain I/O or SPI serial data input selected by HW_SW_CTRL mode |
| 26 | SCL/SCK | input | I2C serial clock open-drain input or SPI serial clock input selected by HW_SW_CTRL mode |
| 27 | VDD_PLL1 | power_in | 3.3V core power supply for APLL1, APLL2, and digital block; bypass with 10µF capacitor |
| 28 | CAP_PLL1 | passive | External bypass capacitor for APLL1 LDO regulator; recommend 10µF |
| 29 | LF1 | passive | External loop filter capacitor for APLL1; recommend 0.47µF for 1.0kHz loop bandwidth |
| 30 | GPIO2/SDO/FINC | bidirectional | SPI serial data output or DPLL DCO frequency increment input in pin control mode |
| 31 | XO_P | input | Oscillator input positive terminal; 10MHz to 100MHz differential or single-ended signal |
| 32 | XO_N | input | Oscillator input negative terminal; 10MHz to 100MHz differential or single-ended signal |
| 33 | VDD_XO | power_in | 3.3V core power supply for XO input; bypass with 10µF capacitor |
| 34 | LF2 | passive | External loop filter capacitor for APLL2; recommend 0.1µF for 500kHz loop bandwidth |
| 35 | CAP_PLL2 | passive | External bypass capacitor for APLL2 LDO regulator; recommend 10µF |
| 36 | VDD_PLL2 | power_in | 3.3V core power supply for APLL2; bypass with 10µF capacitor |
| 37 | VDDO_4 | power_in | Output power supply for OUT4-OUT7 (1.8V/2.5V/3.3V); bypass with 0.1µF capacitor |
| 38 | OUT4_N | output | Clock output 4 negative; differential/HCSL (2MHz-800MHz) or 1.8V LVCMOS format |
| 39 | OUT4_P | output | Clock output 4 positive; differential/HCSL (2MHz-800MHz) or 1.8V LVCMOS format |
| 40 | VDDO_5 | power_in | Output power supply for OUT4-OUT7 (1.8V/2.5V/3.3V); bypass with 0.1µF capacitor |
| 41 | OUT5_N | output | Clock output 5 negative; differential/HCSL (2MHz-800MHz) or 1.8V LVCMOS format |
| 42 | OUT5_P | output | Clock output 5 positive; differential/HCSL (2MHz-800MHz) or 1.8V LVCMOS format |
| 43 | VDDO_6 | power_in | Output power supply for OUT4-OUT7 (1.8V/2.5V/3.3V); bypass with 0.1µF capacitor |
| 44 | OUT6_N | output | Clock output 6 negative; AC-LVDS/CML/LVPECL/HCSL format, 2MHz to 800MHz |
| 45 | OUT6_P | output | Clock output 6 positive; AC-LVDS/CML/LVPECL/HCSL format, 2MHz to 800MHz |
| 46 | VDDO_7 | power_in | Output power supply for OUT4-OUT7 (1.8V/2.5V/3.3V); bypass with 0.1µF capacitor |
| 47 | OUT7_N | output | Clock output 7 negative; differential/HCSL (2MHz-800MHz) or 1.8V LVCMOS format |
| 48 | OUT7_P | output | Clock output 7 positive; differential/HCSL (2MHz-800MHz) or 1.8V LVCMOS format |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Clock/Timing |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
LMK05318RGZT - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
lmk05318rgzt-etched.step/lmk05318rgzt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lmk05318rgzt.step/lmk05318rgzt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (83 pp, sha256
72f9aafb7d60fe72, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).