component
MC14082BDR2G
Public Made by Adomby adom
onsemi Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC14082BDR2G
onsemi · Gates · SOIC-14
MC14082BDR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Buffered output of gate A (4-input AND), capable of driving two low-power TTL loads; input/output limited to ±10 mA per pin. |
| 2 | IN 1A | input | Gate A input 1; unused AND inputs must be tied to VDD and held within VSS to VDD. |
| 3 | IN 2A | input | Gate A input 2; unused AND inputs must be tied to VDD and held within VSS to VDD. |
| 4 | IN 3A | input | Gate A input 3; unused AND inputs must be tied to VDD and held within VSS to VDD. |
| 5 | IN 4A | input | Gate A input 4; unused AND inputs must be tied to VDD and held within VSS to VDD. |
| 6 | NC | unconnected | No connection. |
| 7 | VSS | power_in | Negative supply / ground (VSS) for all devices in the series. |
| 8 | NC | unconnected | No connection. |
| 9 | IN 1B | input | Gate B input 1; unused AND inputs must be tied to VDD and held within VSS to VDD. |
| 10 | IN 2B | input | Gate B input 2; unused AND inputs must be tied to VDD and held within VSS to VDD. |
| 11 | IN 3B | input | Gate B input 3; unused AND inputs must be tied to VDD and held within VSS to VDD. |
| 12 | IN 4B | input | Gate B input 4; unused AND inputs must be tied to VDD and held within VSS to VDD. |
| 13 | OUTB | output | Buffered output of gate B (4-input AND), capable of driving two low-power TTL loads; input/output limited to ±10 mA per pin. |
| 14 | VDD | power_in | Positive supply, 3.0 Vdc to 18 Vdc (absolute maximum -0.5 to +18.0 V referenced to VSS). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage Range | VDD | -0.5 | 18 | V | Voltages referenced to VSS | 1 | |
| Input or Output Voltage Range | Vin, Vout | -0.5 | V | DC or Transient; max VDD + 0.5 | 1 | ||
| Input or Output Current per Pin | Iin, Iout | -10 | 10 | mA | DC or Transient, per pin | 1 | |
| Power Dissipation per Package | PD | 500 | mW | Note 1; derate -7.0 mW/C from 65C to 125C | 1 | ||
| Ambient Temperature Range | TA | -55 | 125 | °C | 1 | ||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 1 | ||
| Lead Temperature | TL | 260 | °C | 8-second soldering | 1 | ||
| ESD Withstand Voltage Human Body Model | VESD | 3000 | V | HBM, > 3000 | 1 | ||
| ESD Withstand Voltage Machine Model | VESD | 300 | V | MM, > 300 | 1 | ||
| Supply Voltage Range | VDD | 3 | 18 | Vdc | Features | 1 | |
| Output Voltage 0 Level | VOL | 0.05 | Vdc | Vin = VDD or 0; VDD=5.0/10/15 V; -55C, 25C, 125C | 3 | ||
| Output Voltage 1 Level | VOH | 4.95 | 5 | Vdc | Vin = 0 or VDD; VDD=5.0 V; -55C, 25C, 125C | 3 | |
| Output Voltage 1 Level | VOH | 9.95 | 10 | Vdc | Vin = 0 or VDD; VDD=10 V; -55C, 25C, 125C | 3 | |
| Output Voltage 1 Level | VOH | 14.95 | 15 | Vdc | Vin = 0 or VDD; VDD=15 V; -55C, 25C, 125C | 3 | |
| Input Voltage 0 Level | VIL | 2.25 | 1.5 | Vdc | VDD=5.0 V, VO = 4.5 or 0.5 Vdc | 3 | |
| Input Voltage 0 Level | VIL | 4.5 | 3 | Vdc | VDD=10 V, VO = 9.0 or 1.0 Vdc | 3 | |
| Input Voltage 0 Level | VIL | 6.75 | 4 | Vdc | VDD=15 V, VO = 13.5 or 1.5 Vdc | 3 | |
| Input Voltage 1 Level | VIH | 3.5 | 2.75 | Vdc | VDD=5.0 V, VO = 0.5 or 4.5 Vdc | 3 | |
| Input Voltage 1 Level | VIH | 7 | 5.5 | Vdc | VDD=10 V, VO = 1.0 or 9.0 Vdc | 3 | |
| Input Voltage 1 Level | VIH | 11 | 8.25 | Vdc | VDD=15 V, VO = 1.5 or 13.5 Vdc | 3 | |
| Output Drive Current Source | IOH | -3 | -4.2 | mAdc | VOH = 2.5 Vdc, VDD=5.0 V, -55C (25C min -2.4; 125C min -1.7) | 3 | |
| Output Drive Current Source | IOH | -0.64 | -0.88 | mAdc | VOH = 4.6 Vdc, VDD=5.0 V, -55C (25C min -0.51; 125C min -0.36) | 3 | |
| Output Drive Current Source | IOH | -1.6 | -2.25 | mAdc | VOH = 9.5 Vdc, VDD=10 V, -55C (25C min -1.3; 125C min -0.9) | 3 | |
| Output Drive Current Source | IOH | -4.2 | -8.8 | mAdc | VOH = 13.5 Vdc, VDD=15 V, -55C (25C min -3.4; 125C min -2.4) | 3 | |
| Output Drive Current Sink | IOL | 0.64 | 0.88 | mAdc | VOL = 0.4 Vdc, VDD=5.0 V, -55C (25C min 0.51; 125C min 0.36) | 3 | |
| Output Drive Current Sink | IOL | 1.6 | 2.25 | mAdc | VOL = 0.5 Vdc, VDD=10 V, -55C (25C min 1.3; 125C min 0.9) | 3 | |
| Output Drive Current Sink | IOL | 4.2 | 8.8 | mAdc | VOL = 1.5 Vdc, VDD=15 V, -55C (25C min 3.4; 125C min 2.4) | 3 | |
| Input Current | Iin | -0.1 | 0.1 | Adc | VDD=15 V, -55C (25C ±0.1 max, typ ±0.00001; 125C ±1.0) | 3 | |
| Input Capacitance | Cin | 5 | 7.5 | pF | Vin = 0, 25C | 3 | |
| Quiescent Current (Per Package) | IDD | 0.0005 | 0.25 | Adc | VDD=5.0 V, -55C and 25C (125C max 7.5) | 3 | |
| Quiescent Current (Per Package) | IDD | 0.001 | 0.5 | Adc | VDD=10 V, -55C and 25C (125C max 15) | 3 | |
| Quiescent Current (Per Package) | IDD | 0.0015 | 1 | Adc | VDD=15 V, -55C and 25C (125C max 30) | 3 | |
| Output Rise Time | tTLH | 100 | 200 | ns | VDD=5.0 V, CL=50 pF, TA=25C | 4 | |
| Output Rise Time | tTLH | 50 | 100 | ns | VDD=10 V, CL=50 pF, TA=25C | 4 | |
| Output Rise Time | tTLH | 40 | 80 | ns | VDD=15 V, CL=50 pF, TA=25C | 4 | |
| Output Fall Time | tTHL | 100 | 200 | ns | VDD=5.0 V, CL=50 pF, TA=25C | 4 | |
| Output Fall Time | tTHL | 50 | 100 | ns | VDD=10 V, CL=50 pF, TA=25C | 4 | |
| Output Fall Time | tTHL | 40 | 80 | ns | VDD=15 V, CL=50 pF, TA=25C | 4 | |
| Propagation Delay Time (all other 2,3,4 input gates) | tPLH, tPHL | 160 | 300 | ns | VDD=5.0 V, CL=50 pF, TA=25C | 4 | |
| Propagation Delay Time (all other 2,3,4 input gates) | tPLH, tPHL | 65 | 130 | ns | VDD=10 V, CL=50 pF, TA=25C | 4 | |
| Propagation Delay Time (all other 2,3,4 input gates) | tPLH, tPHL | 50 | 100 | ns | VDD=15 V, CL=50 pF, TA=25C | 4 |
CAD (KiCad official)
- Symbol:
MC14082BDR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc14082bdr2g-etched.step/mc14082bdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc14082bdr2g.step/mc14082bdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (13 pp, sha256
9a4857efa55d976b, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).