component
CM1341-LAT
Public Made by Adomby adom
iCM(创芯微) Battery Management, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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README
markdownCM1341-LAT
iCM(创芯微) · Battery Management · TSSOP-16
CM1341-LAT from iCM(创芯微), in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Positive supply input and positive-voltage connection for battery cell 1; absolute maximum rating is VSS-0.3 V to VSS+40 V. |
| 2 | VNC | passive | Battery cell 1 positive-voltage connection as labelled in the pin table; the datasheet gives no separate function or rating for this pin. |
| 3 | VNC | passive | Battery cell 1 positive-voltage connection as labelled in the pin table; the datasheet gives no separate function or rating for this pin. |
| 4 | VNC | passive | Battery cell 1 positive-voltage connection as labelled in the pin table; the datasheet gives no separate function or rating for this pin. |
| 5 | VC1 | passive | Battery cell 1 positive-voltage connection used for cell voltage sensing; cell-input absolute maximum rating is VSS-0.3 V to VSS+40 V. |
| 6 | VC2 | passive | Negative terminal of battery cell 1 and positive terminal of battery cell 2 for cell voltage sensing; cell-input absolute maximum rating is VSS-0.3 V to VSS+40 V. |
| 7 | VC3 | passive | Negative terminal of battery cell 2 and positive terminal of battery cell 3 for cell voltage sensing; cell-input absolute maximum rating is VSS-0.3 V to VSS+40 V. |
| 8 | VC4 | passive | Negative terminal of battery cell 3 and positive terminal of battery cell 4 for cell voltage sensing; cell-input absolute maximum rating is VSS-0.3 V to VSS+40 V. |
| 9 | VSS | power_in | Chip ground and negative-voltage connection for battery cell 4; the reference for all pin ratings. |
| 10 | TEC | passive | Discharge over-current delay adjustment pin, where an external capacitor CTEC sets the delay (TEC1 = 10 × CTEC in ms with CTEC in nF); absolute maximum rating is VSS-0.3 V to VSS+5.5 V. |
| 11 | RTS | passive | Connection for the NTC thermistor used for temperature detection; absolute maximum rating is VSS-0.3 V to VCC+0.3 V. |
| 12 | RTV | passive | Connects to a resistor to RTS that sets the protection temperature; absolute maximum rating is VSS-0.3 V to VSS+5.5 V. |
| 13 | VINI | input | Over-current detection input that sees the discharge/charge current sense voltage; absolute maximum rating is VSS-0.3 V to VCC+0.3 V. |
| 14 | DO | output | Discharge MOSFET control output, which turns off the discharge MOS when a fault is detected; absolute maximum rating is VSS-0.3 V to VCC+0.3 V. |
| 15 | CO | output | Charge MOSFET control output, which turns off the charge MOS when a fault is detected; absolute maximum rating is VSS-15 V to VCC+0.3 V. |
| 16 | VM | input | Charger and load detection pin; absolute maximum rating is VSS-15 V to VCC+0.3 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | iCM(创芯微) |
| Package | TSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Normal operating current | IVCC | 10 | 15 | μA | Ta=+25°C; VCn-VCn+1=3.5V, VC4-VSS=3.5V | 8 | |
| Overcharge detection voltage, nominal (CM1341-LAT, Table 1) | VOC | 4.175 | V | 4 | |||
| Overcharge detection voltage accuracy (±, printed as VOC ± 0.015 V) | VOC | -0.015 | 0.015 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC4-VSS=3.5→4.4V | 8 | |
| Overcharge release voltage, nominal (CM1341-LAT, Table 1) | VOCR | 4.075 | V | 4 | |||
| Overcharge release voltage accuracy (±, printed as VOCR ± 0.030 V) | VOCR | -0.03 | 0.03 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC4-VSS=4.4→3.5V | 8 | |
| Overcharge protection delay | TOC | 0.7 | 1 | 1.3 | s | Ta=+25°C; VC4-VSS=3.5→4.4V | 8 |
| Overcharge release delay | TOCR | 128 | 256 | 384 | ms | Ta=+25°C; VC4-VSS=4.4→3.5V | 8 |
| Balance start voltage, nominal (CM1341-LAT, Table 1) | VBAL | 4.05 | V | 4 | |||
| Balance start voltage accuracy (±, printed as VBAL ± 0.025 V) | VBAL | -0.025 | 0.025 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC4-VSS=3.5→4.4V | 8 | |
| Overdischarge protection voltage, nominal (CM1341-LAT, Table 1) | VOD | 2.7 | V | 4 | |||
| Overdischarge protection voltage accuracy (±, printed as VOD ± 0.050 V) | VOD | -0.05 | 0.05 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC4-VSS=3.5→2.0V | 8 | |
| Overdischarge release voltage, nominal (CM1341-LAT, Table 1) | VODR | 3 | V | 4 | |||
| Overdischarge release voltage accuracy (±, printed as VODR ± 0.080 V) | VODR | -0.08 | 0.08 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC4-VSS=2.0→3.5V | 8 | |
| Overdischarge protection delay | TOD | 0.7 | 1 | 1.3 | s | Ta=+25°C; VC4-VSS=3.5→2.0V | 8 |
| Overdischarge release delay | TODR | 128 | 256 | 384 | ms | Ta=+25°C; VC4-VSS=2.0→3.5V | 8 |
| Low-voltage charge inhibit voltage | VLV | 1.2 | 1.5 | 1.8 | V | Ta=+25°C; VC4-VSS=3.5→1.2V | 8 |
| Low-voltage charge inhibit release voltage | VLVR | 1.22 | 1.52 | 1.82 | V | Ta=+25°C; VC4-VSS=1.2→3.5V | 8 |
| Low-voltage charge inhibit delay | TLV | 0.7 | 1 | 1.3 | s | Ta=+25°C; VC4-VSS=3.5→1.2V | 8 |
| Low-voltage charge inhibit release delay | TLVR | 128 | 256 | 384 | ms | Ta=+25°C; VC4-VSS=1.2→3.5V | 8 |
| Discharge overcurrent 1 voltage, nominal (CM1341-LAT, Table 1) | VEC1 | 0.05 | V | 4 | |||
| Discharge overcurrent 1 voltage accuracy (±, printed as VEC1 ± 0.005 V) | VEC1 | -0.005 | 0.005 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC4-VSS=3.5V, VINI=0→0.18V | 8 | |
| Discharge overcurrent 1 delay | TEC1 | 0.5 | 1 | 1.5 | s | Ta=+25°C; VINI=0→0.18V, CTEC=0.1μF (±1%) | 8 |
| Discharge overcurrent 2 voltage, nominal (CM1341-LAT, Table 1) | VEC2 | 0.1 | V | 4 | |||
| Discharge overcurrent 2 voltage accuracy (±15 %, printed as VEC285% to VEC2115%) | VEC2 | -15 | 15 | % | Ta=+25°C; VCn-VCn+1=3.5V, VC4-VSS=3.5V, VINI=0→0.35V | 8 | |
| Discharge overcurrent 2 delay | TEC2 | 50 | 100 | 150 | ms | Ta=+25°C; VINI=0→0.35V, CTEC=0.1μF (±1%) | 8 |
| Short-circuit protection voltage, nominal (CM1341-LAT, Table 1) | VSHORT | 0.2 | V | 4 | |||
| Short-circuit protection delay | TSHORT | 100 | 300 | 500 | μs | Ta=+25°C; VINI=0→0.8V | 9 |
| Discharge overcurrent release delay | TECR | 22 | 32 | 42 | ms | Ta=+25°C; VINI=0.8→0V | 9 |
| Charge overcurrent protection voltage, nominal (CM1341-LAT, Table 1) | VCHA | -0.025 | V | 4 | |||
| Charge overcurrent voltage accuracy for VCHA ≥ -0.050 V (±, printed as VCHA ± 0.005 V) | VCHA | -0.005 | 0.005 | V | Ta=+25°C; VCn-VCn+1=3.5V, VC4-VSS=3.5V, VINI=0→-1.0V | 9 | |
| Charge overcurrent protection delay | TCHA | 180 | 256 | 332 | ms | Ta=+25°C; VINI=0→-1.0V | 9 |
| Charge overcurrent release delay | TCHAR | 45 | 64 | 83 | ms | Ta=+25°C; VINI=-1V→0V | 9 |
| Open-wire protection delay | TOW | 4 | s | Ta=+25°C; CVC1~4=0.1μF | 9 | ||
| Charge high-temperature protection temperature accuracy (±3 °C, printed as TCH ± 3) | TCH | -3 | 3 | °C | Ta=+25°C; RNTC=100k→10k | 9 | |
| Charge high-temperature release temperature accuracy (±3 °C) | TCHR | -3 | 3 | °C | Ta=+25°C; RNTC=10k→100k | 9 | |
| Discharge high-temperature protection temperature accuracy (±3 °C) | TDH | -3 | 3 | °C | Ta=+25°C; RNTC=100k→10k | 9 | |
| Discharge high-temperature release temperature accuracy (±3 °C) | TDHR | -3 | 3 | °C | Ta=+25°C; RNTC=10k→100k | 9 | |
| Charge high-temperature protection delay | DTCH | 0.7 | 1 | 1.3 | s | Ta=+25°C; RNTC=100k→10k | 9 |
| Charge high-temperature release delay | DTCHR | 90 | 128 | 166 | ms | Ta=+25°C; RNTC=10k→100k | 9 |
| Discharge high-temperature protection delay | DTDH | 0.7 | 1 | 1.3 | s | Ta=+25°C; RNTC=100k→10k | 9 |
| Discharge high-temperature release delay | DTDHR | 90 | 128 | 166 | ms | Ta=+25°C; RNTC=10k→100k | 9 |
| Charge low-temperature protection temperature accuracy (±3 °C) | TCL | -3 | 3 | °C | Ta=+25°C; RNTC=100k→3M | 9 | |
| Charge low-temperature release temperature accuracy (±3 °C) | TCLR | -3 | 3 | °C | Ta=+25°C; RNTC=3M→100k | 9 | |
| Discharge low-temperature protection temperature accuracy (±3 °C) | TDL | -3 | 3 | °C | Ta=+25°C; RNTC=100k→3M | 9 | |
| Discharge low-temperature release temperature accuracy (±3 °C) | TDLR | -3 | 3 | °C | Ta=+25°C; RNTC=3M→100k | 10 | |
| Charge low-temperature protection delay | DTCL | 0.7 | 1 | 1.3 | s | Ta=+25°C; RNTC=100k→3M | 10 |
| Charge low-temperature release delay | DTCLR | 90 | 128 | 166 | ms | Ta=+25°C; RNTC=3M→100k | 10 |
| Discharge low-temperature protection delay | DTDL | 0.7 | 1 | 1.3 | s | Ta=+25°C; RNTC=100k→3M | 10 |
| Discharge low-temperature release delay | DTDLR | 90 | 128 | 166 | ms | Ta=+25°C; RNTC=3M→100k | 10 |
| Discharge state detection voltage | VSTS | 1 | 4 | 7 | mV | Ta=+25°C; VINI=0→10mV | 10 |
| Discharge state detection delay | TSTS | 3 | 4.5 | 6 | ms | Ta=+25°C; VINI=0→10mV | 10 |
| Sleep delay | TSLP | 22 | 32 | 42 | s | Ta=+25°C; VC4-VSS=3.5→1.5V | 10 |
| Supply voltage VCC (relative to VSS, VSS-0.3 ~ VSS+40) | VCC | -0.3 | 40 | V | 7 | ||
| Cell input voltage VCn (relative to VSS, VSS-0.3 ~ VSS+40) | VCELL | -0.3 | 40 | V | 7 | ||
| Input voltage RTV, TEC (relative to VSS, VSS-0.3 ~ VSS+5.5) | VIN1 | -0.3 | 5.5 | V | 7 | ||
| Input voltage VM, CO (relative to VSS, VSS-15 ~ VCC+0.3; upper limit not numeric) | VIN2 | -15 | V | 7 | |||
| Input voltage DO, RTS, VINI (relative to VSS, VSS-0.3 ~ VCC+0.3; upper limit not numeric) | VIN3 | -0.3 | V | 7 | |||
| Operating ambient temperature | TOPR | -40 | 85 | °C | 7 | ||
| Storage temperature range | TSTG | -55 | 125 | °C | 7 |
CAD (KiCad official)
- Symbol:
CM1341-LAT - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cm1341-lat-etched.step/cm1341-lat-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cm1341-lat.step/cm1341-lat.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: iCM(创芯微) datasheet (22 pp, sha256
3c1bb3810ab4a56c, retrieved 2026-11-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).