component
DP83TD510ERHBR
Public Made by Adomby adom
Texas Instruments Ethernet ICs, HVQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDP83TD510ERHBR
Texas Instruments · Ethernet ICs · HVQFN-32-EP(5x5)
DP83TD510ERHBR from Texas Instruments, in a HVQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVDD | power_in | 1.0V digital supply; short to CEXT (pin 2) for single-supply operation, or connect an external 1.0V supply for ultra-low-power dual-supply operation (recommended 0.90 to 1.1V). |
| 2 | CEXT | passive | External capacitor for the internal LDO; connect a 0.01uF capacitor and short to pin 1 for single supply, leave unconnected for dual supply. |
| 3 | VDDA | power_in | Analog supply: 3.3V (3.0 to 3.6V) supports 2.4V p2p and 1V p2p modes, 1.8V (1.62 to 1.98V) supports 1V p2p mode only. |
| 4 | TX+ | output | Differential transmit output (PMD) configured as 2.4V p2p or 1V p2p according to PHY configuration and auto-negotiation. |
| 5 | RX+ | input | Differential receive input that is automatically configured to accept 2.4V p2p or 1V p2p mode. |
| 6 | RX- | input | Differential receive input that is automatically configured to accept 2.4V p2p or 1V p2p mode. |
| 7 | TX- | output | Differential transmit output (PMD) configured as 2.4V p2p or 1V p2p according to PHY configuration and auto-negotiation. |
| 8 | GPIO2/Strap10 | bidirectional | Register-configurable GPIO with forced PU/PD strap (Strap10) that selects termination: 0 = receiver with 50 ohm tap resistor (recommended), 1 = tap resistor below 40 ohm; internal pull-down in all states. |
| 9 | XO | output | Crystal output for the reference clock; used only with a crystal and left floating when a CMOS oscillator drives XI. |
| 10 | XI/50MHzIn | input | Crystal/oscillator input clock: 25MHz +/-50ppm for MII and RMII master, 50MHz +/-50ppm CMOS oscillator for RMII slave. |
| 11 | MDIO | bidirectional | Bidirectional management data I/O that requires an external 2.2k to 4.0k ohm pull-up resistor. |
| 12 | MDC | input | Management data clock for MDIO serial management, asynchronous to MAC clocks, maximum 1.75MHz. |
| 13 | RX_D3/Strap1 | bidirectional | Receive data bit 3 (nibble RX_D[3:0] in MII mode, synchronous to RX_CLK); latched at reset as PHY address bit 3 strap, internal pull-down. |
| 14 | RX_D2/Strap2 | bidirectional | Receive data bit 2 (MII/RGMII); strap selects pin 18 as CRS_DV (0, default) or RX_DV (1, RMII repeater/media converter), internal pull-down. |
| 15 | RX_D1/Strap3 | bidirectional | Receive data bit 1 (RX_D[1:0] in RMII); strap with Strap8 selects MAC mode (MII, RMII master, RGMII, RMII slave), internal pull-down. |
| 16 | RX_D0 | bidirectional | Receive data bit 0 (RX_D[1:0] in RMII); latched at reset as PHY address bit 2 strap, internal pull-down. |
| 17 | VDDIO | power_in | I/O supply of 3.3V, 2.5V or 1.8V (1.62 to 3.6V across options); see decoupling requirements in the application section. |
| 18 | RX_DV/CRS_DV/Strap5 | bidirectional | Receive data valid (MII) or CRS_DV (RMII), RGMII RX_CTRL; strap selects CLKOUT 25MHz (0) or LED_1 (1) on pin 30, internal pull-down. |
| 19 | RX_CLK/50MHz_RMII_M | bidirectional | MII/RGMII receive clock (2.5MHz at 10Mbps) and 50MHz reference clock output in RMII master mode; unused input with pull-down in RMII slave mode. |
| 20 | RX_ER/Strap6 | bidirectional | Receive error indication in MII and RMII modes, unused in RGMII; latched at reset as PHY address bit 1 strap, internal pull-down. |
| 21 | PWDN/INT_N | bidirectional | Active-low power-down (default) or interrupt pin; open-drain output with weak internal 9.5k ohm pull-up, may need an external pull-up. |
| 22 | TX_CLK | bidirectional | MII transmit clock output (2.5MHz at 10Mbps) or RGMII transmit clock input from MAC (2.5MHz at 10Mbps); unused in RMII. |
| 23 | TX_EN | input | Transmit enable (TX_CTRL in RGMII) indicating valid data on TX_D[3:0] (MII) or TX_D[1:0] (RMII); active high with internal pull-down. |
| 24 | TX_D0 | input | Transmit data bit 0 from the MAC, synchronous to TX_CLK (MII), CLKOUT50M (RMII master) or the reference clock (RMII slave); internal pull-down. |
| 25 | TX_D1 | input | Transmit data bit 1 from the MAC, synchronous to TX_CLK (MII), CLKOUT50M (RMII master) or the reference clock (RMII slave); internal pull-down. |
| 26 | TX_D2 | input | Transmit data bit 2 from the MAC (MII and RGMII nibble TX_D[3:0]); internal pull-down. |
| 27 | TX_D3 | input | Transmit data bit 3 from the MAC (MII and RGMII nibble TX_D[3:0]); internal pull-down. |
| 28 | LED_2/TX_ER/Strap7 | bidirectional | LED_2 by default (on when link is 10M short reach), configurable as GPIO or TX_ER; Strap7 reach selection: 0 = 2.4V and 1V p2p, 1 = 1V p2p only. |
| 29 | LED_0/Strap8 | bidirectional | Link/activity LED (on for link, blinks on TX/RX activity), also usable as GPIO; Strap8 with Strap3 selects MAC mode. |
| 30 | CLKOUT/LED_1 | output | Provides 25MHz reference CLKOUT by default, configurable as LED_1 (on when link is 10M long reach) by strap or register; clock is unaffected by reset when CLK_OUT. |
| 31 | RST_N | input | Active-low reset input; hold low at least 25us to reset, which rescans straps and resets all registers to defaults; internal pull-up. |
| 32 | GPIO1/Strap9 | bidirectional | General-purpose input or output; latched at reset as PHY address bit 0 strap, internal pull-down. |
| 33 | EP | power_in | Exposed die attach pad (DAP) connected to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVQFN-32-EP(5x5) |
| Category | Interface ICs |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output differential voltage 1V p2p | Vod | 0.85 | 1 | 1.05 | V | IEEE Tx conformance (10BaseT1L external termination), 1V p2p | 8 |
| Output differential voltage 2.4V p2p | Vod | 2.04 | 2.4 | 2.56 | V | IEEE Tx conformance (10BaseT1L external termination), 2.4V p2p | 8 |
| DVDD1.0 current, dual analog supply, 1V p2p | DVDD1.0 | 3.5 | 7.5 | mA | Typ: 100% traffic, random size 64 to 1512 bytes, random content, 25°C; Max: across process, voltage and temperature | 9 | |
| AVDD1.8 current, dual analog supply, 1V p2p | AVDD1.8 | 16 | 21.5 | mA | Typ: 100% traffic, random size 64 to 1512 bytes, random content, 25°C; Max: across process, voltage and temperature | 9 | |
| DVDD1.0 current, reset | DVDD1.0 | 6 | mA | Reset | 9 | ||
| AVDD1.8 current, reset | AVDD1.8 | 5 | mA | Reset | 9 | ||
| DVDD1.0 current, IEEE power down | DVDD1.0 | 5 | mA | IEEE power down | 9 | ||
| AVDD1.8 current, IEEE power down | AVDD1.8 | 5 | mA | IEEE power down | 9 | ||
| DVDD1.0 current, dual analog supply, 2.4V p2p | DVDD1.0 | 3.5 | 7 | mA | Typ: 100% traffic, random size 64 to 1512 bytes, random content, 25°C; Max: across process, voltage and temperature | 9 | |
| AVDD3.3 current, dual analog supply, 2.4V p2p | AVDD3.3 | 22 | 32 | mA | Typ: 100% traffic, random size 64 to 1512 bytes, random content, 25°C; Max: across process, voltage and temperature | 9 | |
| AVDD3.3 current, reset, 2.4V p2p | AVDD3.3 | 5 | mA | Reset | 9 | ||
| AVDD3.3 current, single analog supply, 1V p2p, 200 m | AVDD3.3 | 19 | 26 | mA | Temperature -40 to 105°C; Typ: 100% traffic, random size 64 to 1512 bytes, 25°C; Max: across process, voltage and temperature | 9 | |
| AVDD1.8 current, single analog supply, 1V p2p, 200 m | AVDD1.8 | 19 | 26.5 | mA | Temperature -40 to 105°C; Typ: 100% traffic, random size 64 to 1512 bytes, 25°C; Max: across process, voltage and temperature | 9 | |
| AVDD3.3 current, single analog supply, 2.4V p2p, 1000 m | AVDD3.3 | 26 | 38 | mA | Temperature -40 to 105°C; Typ: 100% traffic, random size 64 to 1512 bytes, 25°C; Max: across process, voltage and temperature | 9 | |
| VDDIO1.8 current (MII interface) | VDDIO1.8 | 2.75 | 4 | mA | Typ: 100% traffic, random size 64 to 1512 bytes, 25°C; Max: across process, voltage and temperature | 9 | |
| DVDD 1.0 supply voltage | DVDD | 0.9 | 1 | 1.1 | V | 7 | |
| VDDA 1.8 analog supply | VDDA | 1.62 | 1.8 | 1.98 | V | 7 | |
| VDDA 3.3 analog supply | VDDA | 3 | 3.3 | 3.6 | V | 7 | |
| VDDIO supply, 1.8V operation | VDDIO | 1.62 | 1.8 | 1.98 | V | 1.8V operation | 7 |
| VDDIO supply, 2.5V operation | VDDIO | 2.25 | 2.5 | 2.75 | V | 2.5V operation | 7 |
| VDDIO supply, 3.3V operation | VDDIO | 3 | 3.3 | 3.6 | V | 3.3V operation | 7 |
| Operating ambient temperature | TA | -40 | 105 | °C | 7 | ||
| DVDD 1.0 supply abs max | DVDD | -0.3 | 1.4 | V | 7 | ||
| VDDA 1.8 supply abs max | VDDA | -0.3 | 4 | V | 7 | ||
| VDDA 3.3 supply abs max | VDDA | -0.3 | 4 | V | 7 | ||
| VDDIO (3.3) abs max | VDDIO | -0.3 | 4 | V | 7 | ||
| VDDIO (2.5) abs max | VDDIO | -0.3 | 3 | V | 7 | ||
| VDDIO (1.8) abs max | VDDIO | -0.3 | 2.1 | V | 7 | ||
| MDI pins voltage (Tx+, Tx-, Rx+, Rx-) | -0.3 | 4 | V | 7 | |||
| Digital I/O pin voltage | -0.3 | 0.3 | V | Max is VDDIO + 0.3 V; TX_D[0:3], RX_D[0:3], TX_CLK, RX_CLK, TX_EN, RX_DV, RX_ER, MDIO, MDC, LED0-2 | 7 | ||
| INT/PWDN, RESET pin voltage | -0.3 | 0.3 | V | Max is VDDIO + 0.3 V | 7 | ||
| XI oscillator input voltage | -0.3 | 0.3 | V | Max is VDDIO + 0.3 V | 7 | ||
| ESD HBM, all pins except MDI | V(ESD) | -2000 | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001 | 7 | |
| ESD HBM, MDI pins | V(ESD) | -6000 | 6000 | V | HBM per ANSI/ESDA/JEDEC JS-001 | 7 | |
| ESD CDM, all pins | V(ESD) | -1000 | 1000 | V | CDM per JESD22-C101 | 7 | |
| Junction-to-ambient thermal resistance | RθJA | 52 | °C/W | 32-pin QFN | 8 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 42 | °C/W | 32-pin QFN | 8 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 10 | °C/W | 32-pin QFN | 8 | ||
| Junction-to-board thermal resistance | RθJB | 30 | °C/W | 32-pin QFN | 8 | ||
| Junction-to-top characterization parameter | ΨJT | 2 | °C/W | 32-pin QFN | 8 | ||
| Junction-to-board characterization parameter | ΨJB | 30 | °C/W | 32-pin QFN | 8 |
CAD (KiCad official)
- Symbol:
DP83TD510ERHBR - Footprint:
Package_DFN_QFN:HVQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm - 3D model: HVQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
dp83td510erhbr-etched.step/dp83td510erhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dp83td510erhbr.step/dp83td510erhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (94 pp, sha256
5a6ce942292a529e, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).