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Contents

README

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PCM3008T

Texas Instruments · Audio Interface ICs · TSSOP-16

PCM3008T from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCOM passive ADC/DAC common-voltage decouple pin that must be bypassed to GND with a 0.1 µF ceramic and a 1 µF or larger chemical capacitor placed as close to the pin as possible.
2 VINR input ADC single-ended analog input for the right channel, with 30 kΩ input impedance and 0.6 VCC Vp-p input voltage, AC-coupled through a 0.47 µF to 4.7 µF capacitor.
3 VINL input ADC single-ended analog input for the left channel, with 30 kΩ input impedance and 0.6 VCC Vp-p input voltage, AC-coupled through a 0.47 µF to 4.7 µF capacitor.
4 GND power_in Ground; the analog and digital grounds are internally tied and VCC must be bypassed to this pin.
5 VCC power_in Power supply, 2.1 V min to 3.6 V max (2.4 V typical), bypassed to GND with 0.1 µF ceramic and 10 µF chemical capacitors as close to the pins as possible.
6 DEM0 input De-emphasis control 0 (Schmitt trigger input, 3.3 V tolerant) that selects the DAC de-emphasis mode together with DEM1; the pin must not be left open.
7 DEM1 input De-emphasis control 1 (Schmitt trigger input, 3.3 V tolerant) that selects the DAC de-emphasis mode together with DEM0; the pin must not be left open.
8 DOUT output ADC serial data output in 16-bit left-justified format, forced to zero during ADC power-down and during the initialization sequence.
9 DIN input DAC serial data input in 16-bit right-justified format (Schmitt trigger input, 3.3 V tolerant), which must not be left open because there is no internal pullup or pulldown.
10 LRCK input Sampling clock (left/right channel) input synchronized to SYSCK (Schmitt trigger input, 3.3 V tolerant), which must not be left open because there is no internal pullup or pulldown.
11 SYSCK input System clock input that must be 256fS, 384fS or 512fS, with minimum 15 ns high and low pulse widths and carefully managed duty cycle and jitter (Schmitt trigger input, 3.3 V tolerant).
12 BCK input Bit clock input supporting 64, 48 or 32 BCK clocks per LRCK period (Schmitt trigger input, 3.3 V tolerant), which must not be left open.
13 PDAD input ADC power-down control, active low: low places the ADC in its lowest power mode, and PDAD and PDDA both low put the device into reset.
14 PDDA input DAC power-down control, active low: low places the DAC in its lowest power mode with VOUT forced to VCOM, and PDAD and PDDA both low put the device into reset.
15 VOUTL output DAC single-ended analog output for the left channel, with 0.6 VCC Vp-p output voltage and a 10 kΩ AC-coupled load impedance.
16 VOUTR output DAC single-ended analog output for the right channel, with 0.6 VCC Vp-p output voltage and a 10 kΩ AC-coupled load impedance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: PCM3008T
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: pcm3008t-etched.step / pcm3008t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pcm3008t.step / pcm3008t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 bac647c89e9d2659, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF