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CY8C4126AXI-S433

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Cypress Semicon CYPRESS, TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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CY8C4126AXI-S433

Cypress Semicon · CYPRESS · TQFP-44(10x10)

CY8C4126AXI-S433 from Cypress Semicon, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSSD power_in Ground for the digital section.
2 P2.0 bidirectional GPIO port 2 bit 0 with SAR mux input sarmux[0], SmartIo[0].io[0], TCPWM line[4], csd.comp and SCB1 I2C/SPI alternate functions.
3 P2.1 bidirectional GPIO port 2 bit 1 with sarmux[1], SmartIo[0].io[1], TCPWM line_compl[4] and SCB1 I2C SDA/SPI MISO alternate functions.
4 P2.2 bidirectional GPIO port 2 bit 2 with sarmux[2], SmartIo[0].io[2] and SCB1 SPI clock alternate function.
5 P2.3 bidirectional GPIO port 2 bit 3 with sarmux[3], SmartIo[0].io[3] and SCB1 SPI select0 alternate function.
6 P2.4 bidirectional GPIO port 2 bit 4 with sarmux[4], SmartIo[0].io[4], TCPWM line[0] and SCB1 SPI select1.
7 P2.5 bidirectional GPIO port 2 bit 5 with sarmux[5], SmartIo[0].io[5], TCPWM line_compl[0] and SCB1 SPI select2.
8 P2.6 bidirectional GPIO port 2 bit 6 with sarmux[6], SmartIo[0].io[6], TCPWM line[1] and SCB1 SPI select3.
9 P2.7 bidirectional GPIO port 2 bit 7 with sarmux[7], SmartIo[0].io[7], TCPWM line_compl[1], lpcomp.comp[0] and SCB2 SPI MOSI.
10 VSSD power_in Ground for the digital section.
11 P3.0 bidirectional GPIO port 3 bit 0 with SmartIo[1].io[0], TCPWM line[0] and SCB1 UART RX/I2C SCL/SPI MOSI alternate functions.
12 P3.1 bidirectional GPIO port 3 bit 1 with SmartIo[1].io[1], TCPWM line_compl[0] and SCB1 UART TX/I2C SDA/SPI MISO alternate functions.
13 P3.2 bidirectional GPIO port 3 bit 2 with SmartIo[1].io[2], TCPWM line[1], SCB1 UART CTS/SPI clock and cpuss.swd_data (SWD data).
14 P3.3 bidirectional GPIO port 3 bit 3 with SmartIo[1].io[3], TCPWM line_compl[1], SCB1 UART RTS/SPI select0 and cpuss.swd_clk (SWD clock).
15 P3.4 bidirectional GPIO port 3 bit 4 with SmartIo[1].io[4], TCPWM line[2], tr_in[6] and SCB1 SPI select1.
16 P3.5 bidirectional GPIO port 3 bit 5 with SmartIo[1].io[5], TCPWM line_compl[2] and SCB1 SPI select2.
17 P3.6 bidirectional GPIO port 3 bit 6 with SmartIo[1].io[6], TCPWM line[3] and SCB1 SPI select3.
18 P3.7 bidirectional GPIO port 3 bit 7 with SmartIo[1].io[7], TCPWM line_compl[3], lpcomp.comp[1] and SCB2 SPI MISO.
19 VDDD power_in Power supply for the digital section.
20 P4.0 bidirectional GPIO port 4 bit 0 with csd.vref_ext and SCB0 UART RX/I2C SCL/SPI MOSI alternate functions.
21 P4.1 bidirectional GPIO port 4 bit 1 with csd.cshieldpads and SCB0 UART TX/I2C SDA/SPI MISO alternate functions.
22 P4.2 bidirectional GPIO port 4 bit 2 with csd.cmodpad, lpcomp.comp[0] and SCB0 UART CTS/SPI clock alternate functions.
23 P4.3 bidirectional GPIO port 4 bit 3 with csd.csh_tank, lpcomp.comp[1] and SCB0 UART RTS/SPI select0 alternate functions.
24 P0.0 bidirectional GPIO port 0 bit 0 with lpcomp.in_p[0], tcpwm.tr_in[0], SCB2 I2C SCL and SCB0 SPI select1.
25 P0.1 bidirectional GPIO port 0 bit 1 with lpcomp.in_n[0], tcpwm.tr_in[1], SCB2 I2C SDA and SCB0 SPI select2.
26 P0.2 bidirectional GPIO port 0 bit 2 with lpcomp.in_p[1] and SCB0 SPI select3.
27 P0.3 bidirectional GPIO port 0 bit 3 with lpcomp.in_n[1] and SCB2 SPI select0.
28 P0.4 bidirectional GPIO port 0 bit 4 with wco.wco_in (32 kHz watch crystal) and SCB1/SCB2 UART RX, SCB1 I2C SCL and SPI MOSI alternate functions.
29 P0.5 bidirectional GPIO port 0 bit 5 with wco.wco_out (32 kHz watch crystal) and SCB1/SCB2 UART TX, SCB1 I2C SDA and SPI MISO alternate functions.
30 P0.6 bidirectional GPIO port 0 bit 6 with srss.ext_clk (external clock input) and SCB1 UART CTS/SPI clock alternate functions.
31 P0.7 bidirectional GPIO port 0 bit 7 with TCPWM line[0] and SCB1 UART RTS/SPI select0 alternate functions.
32 XRES input External reset input pin.
33 VCCD passive Regulated digital supply (1.8 V ± 5%); bypass to ground with a 0.1 µF X5R ceramic or better capacitor and connect to nothing else in Mode 1.
34 VDDD power_in Power supply for the digital section.
35 VDDA power_in Power supply for the analog section.
36 VSSA power_in Ground for the analog section.
37 P1.0 bidirectional GPIO port 1 bit 0 with opamp ctb0_oa0+ input, TCPWM line[2] and SCB0 UART RX/I2C SCL/SPI MOSI alternate functions.
38 P1.1 bidirectional GPIO port 1 bit 1 with opamp ctb0_oa0- input, TCPWM line_compl[2] and SCB0 UART TX/I2C SDA/SPI MISO alternate functions.
39 P1.2 bidirectional GPIO port 1 bit 2 with opamp ctb0_oa0_out, TCPWM line[3] and SCB0 UART CTS/SPI clock alternate functions.
40 P1.3 bidirectional GPIO port 1 bit 3 with opamp ctb0_oa1_out, TCPWM line_compl[3] and SCB0 UART RTS/SPI select0 alternate functions.
41 P1.4 bidirectional GPIO port 1 bit 4 with opamp ctb0_oa1- input and SCB0 SPI select1.
42 P1.5 bidirectional GPIO port 1 bit 5 with opamp ctb0_oa1+ input and SCB0 SPI select2.
43 P1.6 bidirectional GPIO port 1 bit 6 with opamp ctb0_oa0+ input and SCB0 SPI select3.
44 P1.7/VREF bidirectional GPIO port 1 bit 7 with ctb0_oa1+, SAR external reference sar_ext_vref0/1 and SCB2 SPI clock alternate functions.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TQFP-44(10x10)
Category Embedded Processors & Controllers
Pins 44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 22
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 22
Maximum current per GPIO IGPIO_ABS -25 25 mA 22
GPIO injection current IGPIO_injection -0.5 0.5 mA Current injected per pin; Max for VIH > VDDD, Min for VIL < VSS 22
ESD human body model ESD_HBM 2200 V 22
ESD charged device model ESD_CDM 500 V 22
Pin current for latch-up LU -140 140 mA 22
Power supply input voltage VDD 1.8 5.5 V Internally regulated supply 22
Power supply input voltage (VCCD = VDDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 22
Active mode supply current, CPU at 6 MHz IDD5 1.8 2.7 mA Execute from flash; CPU at 6 MHz; Max is at 85°C and 5.5 V 23
Active mode supply current, CPU at 24 MHz IDD8 3 4.75 mA Execute from flash; CPU at 24 MHz 23
Active mode supply current, CPU at 48 MHz IDD11 5.4 6.85 mA Execute from flash; CPU at 48 MHz 23
Sleep mode current, regulator on, 6 MHz IDD17 1.7 2.2 mA I2C wakeup, WDT, and comparators on; 6 MHz; Max is at 85°C and 5.5 V 23
Sleep mode current, regulator on, 12 MHz IDD20 2.2 2.5 mA I2C wakeup, WDT, and comparators on; 12 MHz; Max is at 85°C and 5.5 V 23
Sleep mode current, regulator bypassed, 6 MHz IDD23 0.7 0.9 mA VDDD = 1.71 V to 1.89 V; I2C wakeup, WDT, and comparators on; 6 MHz 23
Sleep mode current, regulator bypassed, 12 MHz IDD23A 1 1.2 mA VDDD = 1.71 V to 1.89 V; I2C wakeup, WDT, and comparators on; 12 MHz 23
Deep Sleep current, VDD 1.8 V to 3.6 V IDD26 2.5 60 µA I2C wakeup and WDT on; Max is at 3.6 V and 85°C 23
Deep Sleep current, VDD 3.6 V to 5.5 V IDD29 2.5 60 µA I2C wakeup and WDT on; Max is at 5.5 V and 85°C 23
Deep Sleep current, regulator bypassed IDD32 2.5 65 µA VDD = VCCD = 1.71 V to 1.89 V; I2C wakeup and WDT on; Max is at 1.89 V and 85°C 23
Supply current while XRES asserted IDD_XR 2 5 mA 23
CPU frequency FCPU 0 48 MHz 1.71 ≤ VDD ≤ 5.5 23
SWDCLK frequency, 3.3 V ≤ VDD ≤ 5.5 V F_SWDCLK1 14 MHz 3.3 V ≤ VDD ≤ 5.5 V; SWDCLK ≤ 1/3 CPU clock frequency 41
SWDCLK frequency, 1.71 V ≤ VDD ≤ 3.3 V F_SWDCLK2 7 MHz 1.71 V ≤ VDD ≤ 3.3 V; SWDCLK ≤ 1/3 CPU clock frequency 41
IMO operating current at 48 MHz IIMO1 250 µA 41
IMO operating current at 24 MHz IIMO2 180 µA 41
IMO frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % At -40°C to 85°C, for industrial temperature range 41
IMO startup time TSTARTIMO 7 µs 42
ILO operating current IILO1 0.3 1.05 µA 42
ILO startup time TSTARTILO1 2 ms 42
ILO duty cycle TILODUTY 40 50 60 % 42
ILO frequency range FILOTRIM1 20 40 80 kHz 42
WCO frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 42
WCO drive level PD 1 µW 42
WCO startup time TSTART 500 ms 43
WCO crystal load capacitance CL 6 12.5 pF 43
WCO operating current (high power mode) IWCO1 8 µA 43
WCO operating current (low power mode) IWCO2 1 µA 43
External clock input frequency ExtClkFreq 0 48 MHz 43
External clock duty cycle ExtClkDuty 45 55 % Measured at VDD/2 43
System clock source switching time TCLKSWITCH 3 4 Periods 43
Max delay added by Smart I/O in Bypass mode PRG_BYPASS 1.6 ns 43
Operating ambient temperature TA -40 25 105 °C 49
Operating junction temperature TJ -40 125 °C 49
Package thermal resistance junction to ambient θJA 57.2 °C/W 44LD TQFP 49
Package thermal resistance junction to case θJC 17.5 °C/W 44LD TQFP 49
Power supply bypass capacitor (external regulator voltage bypass) CEFC 0.1 µF X5R ceramic or better 22
Power supply bypass capacitor CEXC 1 µF 22
Output voltage (for core logic) VCCD 1.8 V 22
Wakeup from Deep Sleep mode TDEEPSLEEP 35 µs 23
RMS jitter at 24 MHz TJITRMSIMO2 145 ps 42

CAD (KiCad official)

  • Symbol: CY8C4126AXI-S433
  • Footprint: Package_QFP:TQFP-44_10x10mm_P0.8mm
  • 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: cy8c4126axi-s433-etched.step / cy8c4126axi-s433-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4126axi-s433.step / cy8c4126axi-s433.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (66 pp, sha256 077139eb014776df, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF