component
TPS560430XDBVR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS560430XDBVR
Texas Instruments · DC-DC Converters · SOT-23-6
TPS560430XDBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CB | passive | Bootstrap capacitor connection for the high-side FET driver. Connect a high-quality 100-nF capacitor from this pin to the SW pin. Absolute max CB-to-SW = 5.5 V. |
| 2 | GND | power_in | Power ground terminal, connected internally to the source of the low-side FET. Connect to system ground and to the ground side of C_IN and C_OUT; path to C_IN must be as short as possible. |
| 3 | FB | input | Feedback input to the converter. Connect a resistor divider from V_OUT to set the output voltage (V_REF = 1.00 V typ; fixed 3.3-V variant uses V_REF = 3.3 V). Never short this terminal to ground during operation. |
| 4 | EN | input | Precision enable input. Do not float. High = on (V_EN_H ~1.23 V), Low = off (V_EN_L ~1.1 V); can be tied to VIN. Adjustable UVLO can be implemented via an external resistor divider. Absolute max = VIN + 0.3 V. |
| 5 | VIN | power_in | Supply input terminal to the internal bias LDO and high-side FET. Operating input range 4 V to 36 V (absolute max 38 V). Connect input bypass capacitors C_IN directly between this pin and GND. |
| 6 | SW | output | Switching output of the converter. Internally connected to the source of the high-side FET and the drain of the low-side FET. Connect to the power inductor. Supports up to 600-mA continuous output current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | PMIC |
| Pins | 6 |
Ordering variants
Same part, different packaging or reel option.
TPS560430XDBVRXFTPS560430XDBVRX3FTPS560430XDBVRXTPS560430XDBVRYTPS560430XDBVRYF
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND | -0.3 | 38 | V | Over recommended TJ range -40 to 125 °C | 4 | ||
| FB to GND | -0.3 | 5.5 | V | Over recommended TJ range -40 to 125 °C | 4 | ||
| SW to GND less than 10 ns transient | -3.5 | 38 | V | Transient, less than 10 ns | 4 | ||
| CB to SW | -0.3 | 5.5 | V | Over recommended TJ range -40 to 125 °C | 4 | ||
| Junction temperature TJ | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| EN to GND | -0.3 | V | Maximum printed as VIN + 0.3 V | 4 | |||
| SW to GND | -0.3 | V | Maximum printed as VIN + 0.3 | 4 | |||
| VIN input voltage | VIN | 4 | 36 | V | VIN to GND | 4 | |
| FB voltage | FB | 0 | 4.5 | V | 4 | ||
| Output voltage | VOUT | 1 | V | Maximum printed as 95% of VIN | 4 | ||
| Output current | IOUT | 0 | 600 | mA | 4 | ||
| Operating junction temperature range | TJ | -40 | 125 | °C | 4 | ||
| EN voltage | EN | 0 | V | Maximum printed as VIN | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 173 | °C/W | DBV (6 pins) package | 4 | ||
| Junction-to-case (TOP) thermal resistance | RθJC_T | 116 | °C/W | DBV (6 pins) package | 4 | ||
| Junction-to-case (BOTTOM) thermal resistance | RθJC_B | 31 | °C/W | DBV (6 pins) package | 4 | ||
| Input voltage operation | VIN | 4 | 36 | V | 5 | ||
| VIN UVLO rising threshold | VIN_UVLO | 3.55 | 3.75 | 4 | V | Rising threshold | 5 |
| VIN UVLO falling threshold | VIN_UVLO | 3.25 | 3.45 | 3.65 | V | Falling threshold | 5 |
| VIN UVLO hysteresis | VIN_UVLO | 0.3 | V | Hysteresis | 5 | ||
| Operating quiescent current (non-switching) | IQ | 80 | 120 | µA | PFM version, VEN = 3.3 V, VFB = 1.1V | 5 | |
| Shutdown current | ISHDN | 3 | 10 | µA | VEN = 0 V | 5 | |
| Enable rising threshold voltage | VEN_H | 1.1 | 1.23 | 1.36 | V | 5 | |
| Enable falling threshold voltage | VEN_L | 0.95 | 1.1 | 1.22 | V | 5 | |
| Enable hysteresis voltage | VEN_HYS | 0.13 | V | 5 | |||
| Leakage current at EN pin | IEN | 10 | 200 | nA | VEN = 3.3 V | 5 | |
| Reference voltage TJ = 25 °C | VREF | 0.995 | 1 | 1.005 | V | TJ = 25 °C | 5 |
| Reference voltage TJ = -40 °C to 125 °C | VREF | 0.985 | 1 | 1.015 | V | TJ = -40 °C to 125 °C | 5 |
| Leakage current at FB pin | IFB | 0.2 | 50 | nA | VFB = 1.2 V | 5 | |
| Peak inductor current limit | IHS_LIMIT | 0.8 | 1.1 | 1.4 | A | 5 | |
| Valley inductor current limit | ILS_LIMIT | 0.62 | 0.8 | 0.98 | A | 5 | |
| Zero cross current | ILS_ZC | 20 | mA | PFM version | 5 | ||
| Hiccup threshold of FB pin | VHICCUP | 40 | % | % of reference voltage | 5 | ||
| High-side MOSFET ON-resistance | RDS_ON_HS | 450 | mΩ | TJ = 25 °C, VIN = 12 V | 5 | ||
| Low-side MOSFET ON-resistance | RDS_ON_LS | 240 | mΩ | TJ = 25 °C, VIN = 12 V | 5 | ||
| Thermal shutdown threshold | TSHDN | 170 | °C | 5 | |||
| Thermal shutdown hysteresis | THYS | 12 | °C | 5 | |||
| Internal soft-start time | TSS | 1.8 | ms | Time of internal reference to increase from 10% to 90% of VREF, VIN = 12 V | 6 | ||
| Hiccup time | THICCUP | 135 | ms | VIN = 12 V | 6 | ||
| Minimum turn-on time | tON_MIN | 60 | ns | IOUT = 600 mA | 6 | ||
| Minimum turn-off time | tOFF_MIN | 100 | ns | IOUT = 600 mA | 6 | ||
| Maximum turn-on time | tON_MAX | 7.5 | µs | 6 | |||
| Oscillator frequency, 1.1-MHz version | fSW | 0.935 | 1.1 | 1.265 | MHz | 1.1-MHz version | 6 |
CAD (KiCad official)
- Symbol:
TPS560430XDBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
tps560430xdbvr-etched.step/tps560430xdbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps560430xdbvr.step/tps560430xdbvr.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tps560430xdbvr.step |
97 KB | You want the bare part, or you mark your own boards. |
tps560430xdbvr-etched.step |
2.8 MB | You want the part with TPS560430XDBVR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 678 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
39cd49d6521912b5, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).