component
CC2340R53E0RKPR
Public Made by Adomby adom
Texas Instruments , VQFN-40(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCC2340R53E0RKPR
Texas Instruments · IC · VQFN-40(5x5)
CC2340R53E0RKPR from Texas Instruments, in a VQFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDR | power_in | Internal regulated supply (VDDR) pin; must stay connected even when DC/DC is unused, with the 10µF capacitor kept on the VDDR net. |
| 2 | DIO8 | bidirectional | Digital I/O (GPIO8) muxable to SPI0SCLK, UART0RTS, T1C0N, I2C0SDA, T0C0N and DTB3. |
| 3 | DIO9 | bidirectional | Digital I/O (GPIO9) muxable to T3C0 and LRFD3. |
| 4 | DIO10 | bidirectional | Digital I/O (GPIO10) muxable to LPCO, T2PE and T3C0N. |
| 5 | DIO11 | bidirectional | Digital I/O (GPIO11) muxable to SPI0CSN, T1C2N, T0C0, LRFD0, SPI0POCI and DTB9. |
| 6 | DIO12 | bidirectional | High-drive digital I/O (GPIO12) muxable to SPI0POCI, SPI0PICO, UART0RXD, T1C1, I2C0SDA and DTB13. |
| 7 | DIO13 | bidirectional | Digital I/O (GPIO13) muxable to SPI0POCI, SPI0PICO, UART0TXD, T0C0N, T1F and DTB4. |
| 8 | VDDS | power_in | Main supply input, operating range 1.71V to 3.8V. |
| 9 | DIO14 | bidirectional | Digital I/O (GPIO14) muxable to T3C2, T1C2N, LRFD5 and T1F. |
| 10 | DIO15 | bidirectional | Digital I/O (GPIO15) muxable to UART0RXD, T2C0N and CKMIN (HFOSC tracking loop input). |
| 11 | DIO16_SWDIO | bidirectional | High-drive digital I/O (GPIO16) that carries serial wire debug data SWDIO, also muxable to SPI0PICO, UART0RXD, I2C0SDA, T1C2, T1C0N and DTB10. |
| 12 | DIO17_SWDCK | bidirectional | High-drive digital I/O (GPIO17) that carries serial wire debug clock SWDCK, also muxable to SPI0SCLK, UART0TXD, I2C0SCL, T1C1N, T0C2 and DTB11. |
| 13 | DIO18 | bidirectional | High-drive digital I/O (GPIO18) muxable to T3C0, LPCO, UART0TXD, SPI0SCLK and DTB12. |
| 14 | DIO19 | bidirectional | High-drive digital I/O (GPIO19) muxable to T3C1, T2PE, SPI0PICO and DTB0. |
| 15 | DIO20_A11 | bidirectional | Digital I/O (GPIO20) with analog capability as ADC channel 11 input (ANA11), muxable to LPCO, UART0, T1C0, SPI0POCI and DTB14. |
| 16 | DIO21_A10 | bidirectional | Digital I/O (GPIO21) with analog capability as ADC channel 10 / low power comparator positive input (ANA10), muxable to UART0CTS, T1C1N, T0C1, SPI0POCI, LRFD1 and DTB15. |
| 17 | VDDS | power_in | Main supply input, operating range 1.71V to 3.8V. |
| 18 | DIO22_A9 | bidirectional | Digital I/O (GPIO22) with analog capability as ADC channel 9 input (ANA9), muxable to T2C0, UART0RXD, T3C1N and DTB1. |
| 19 | DIO23_A8 | bidirectional | Digital I/O (GPIO23) with analog capability as ADC channel 8 / low power comparator input (ANA8), muxable to T2C1 and T3C2N. |
| 20 | DIO24_A7 | bidirectional | High-drive digital I/O (GPIO24) with analog capability as ADC channel 7 / low power comparator positive input (ANA7), muxable to SPI0SCLK, T1C0, T3C0, T0PE, I2C0SCL and DTB5. |
| 21 | DIO25_A6 | bidirectional | Digital I/O (GPIO25) with analog capability as ADC channel 6 input (ANA6), muxable to SPI0POCI, I2C0SCL and T2C2N. |
| 22 | DIO0_A5 | bidirectional | Digital I/O (GPIO0) with analog capability as ADC channel 5 input (ANA5), muxable to SPI0CSN, I2C0SDA and T3C2. |
| 23 | DIO1_A4 | bidirectional | Digital I/O (GPIO1) with analog capability as ADC channel 4 input (ANA4), muxable to T3C1, LRFD7, T1F, UART0RTS and DTB2. |
| 24 | DIO2_A3 | bidirectional | Digital I/O (GPIO2) with analog capability as ADC channel 3 input (ANA3), muxable to T0PE, T2C1N and UART0CTS. |
| 25 | RSTN | bidirectional | Device reset pin, listed as I/O in the pin attributes table. |
| 26 | DIO3_X32P | bidirectional | Digital I/O (GPIO3) that is also 32.768kHz crystal oscillator pin 1 (LFXT_P) or low frequency clock input (LFCI). |
| 27 | DIO4_X32N | bidirectional | Digital I/O (GPIO4) that is also 32.768kHz crystal oscillator pin 2 (LFXT_N), muxable to T0C2N, UART0TXD, LRFD1, SPI0PICO, T0C2 and DTB8. |
| 28 | VDDD | passive | Digital core supply (VDDD) pin, listed as a power pin in the pin attributes table. |
| 29 | DIO5_A2 | bidirectional | Digital I/O (GPIO5) with analog capability as ADC channel 2 input (ANA2), muxable to T2C2 and LRFD6. |
| 30 | DCDC | passive | DC/DC converter switching node; connects through a 10µH inductor to VDDR, and may be left NC when the DC/DC is unused. |
| 31 | VDDS | power_in | Main supply input, operating range 1.71V to 3.8V. |
| 32 | DIO6_A1 | bidirectional | Digital I/O (GPIO6) with analog capability as ADC reference positive terminal or channel 1 input (ANA1), muxable to SPI0CSN, I2C0SCL, T1C2, LRFD2, UART0TXD and DTB6. |
| 33 | DIO7_A0 | bidirectional | Digital I/O (GPIO7) with analog capability as ADC reference negative terminal or channel 0 input (ANA0), muxable to T3C1 and LRFD4. |
| 34 | VDDR | power_in | Internal regulated supply (VDDR) pin; must stay connected even when DC/DC is unused, with the 10µF capacitor kept on the VDDR net. |
| 35 | X48P | passive | 48MHz crystal oscillator pin 1; voltage limited to -0.3V to 1.24V. |
| 36 | X48N | passive | 48MHz crystal oscillator pin 2; voltage limited to -0.3V to 1.24V. |
| 37 | NC | unconnected | No connect pin. |
| 38 | VDDS | power_in | Main supply input, operating range 1.71V to 3.8V. |
| 39 | ANT | passive | 2.4GHz RF antenna connection (integrated balun, 50 Ω single-ended). |
| 40 | RFGND | power_in | RF ground pin. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40(5x5) |
| Category | |
| Pins | 41 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDDS | -0.3 | 4.1 | V | 18 | ||
| Voltage on any digital pin | -0.3 | 4.1 | V | VDDS + 0.3, max 4.1 | 18 | ||
| Voltage on crystal oscillator pins X48P and X48N | -0.3 | 1.24 | V | 18 | |||
| Voltage on ADC input | Vin_adc | 0 | V | max VDDS | 18 | ||
| Input level, RF pins | 5 | dBm | 18 | ||||
| Storage temperature | Tstg | -40 | 150 | °C | 18 | ||
| ESD HBM | VESD | -1000 | 1000 | V | HBM, all pins | 18 | |
| ESD CDM | VESD | -500 | 500 | V | CDM, all pins | 18 | |
| Operating ambient temperature | -40 | 125 | °C | CC2340xxxExxxxx devices (125°C parts) | 18 | ||
| Operating junction temperature | -40 | 125 | °C | CC2340xxxExxxxx devices (125°C parts) | 18 | ||
| Operating supply voltage | VDDS | 1.71 | 3.8 | V | 18 | ||
| Rising supply voltage slew rate | 0 | 100 | mV/µs | 18 | |||
| Falling supply voltage slew rate | 0 | 1 | mV/µs | 18 | |||
| VDDS supply voltage for DCDC operation | 2.2 | 3 | 3.8 | V | Tc = 25°C, DCDC enabled | 18 | |
| VDDS supply voltage for GLDO operation | 1.71 | 3 | 3.8 | V | Tc = 25°C | 19 | |
| Temperature sensor accuracy | -15 | 9 | °C | -40°C to 125°C, 125°C devices, raw output from register | 19 | ||
| Battery monitor range | 1.7 | 3.8 | V | 19 | |||
| Frequency bands | 2360 | 2510 | MHz | 21 | |||
| Junction-to-ambient thermal resistance | RθJA | 31.8 | ℃/W | RKP (VQFN) 40 pins | 21 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 23.1 | ℃/W | RKP (VQFN) 40 pins | 21 | ||
| Junction-to-board thermal resistance | RθJB | 12.7 | ℃/W | RKP (VQFN) 40 pins | 21 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.3 | ℃/W | RKP (VQFN) 40 pins | 21 | ||
| HFXT crystal ESR | ESR | 20 | 60 | Ω | 6pF < CL ≤ 9pF | 26 | |
| HFXT crystal load capacitance | CL | 5 | 7 | 9 | pF | 26 | |
| HFOSC uncalibrated frequency accuracy | -3 | 3 | % | 27 | |||
| HFOSC calibrated frequency accuracy | -0.25 | 0.25 | % | relative to HFXT | 27 | ||
| SPI clock frequency | fSCLK | 12 | MHz | 2.7V ≤ VDDS < 3.8V | 27 | ||
| GPIO pullup current | 39 | 66 | 109 | µA | TA = 25°C, VDDS = 1.8V, Vpad = 0V | 31 | |
| GPIO pullup current | 170 | 262 | 393 | µA | TA = 25°C, VDDS = 3.8V, Vpad = 0V | 32 | |
| GPIO input VIH | VIH | 0.8 | V | TA = 25°C; ×VDDS | 32 | ||
| GPIO input VIL | VIL | 0.2 | V | TA = 25°C; ×VDDS | 32 | ||
| ADC INL | EI | -2 | 2 | LSB | 12-bit mode, VDDS=1.71V-3.8V | 33 | |
| ADC DNL | ED | -1 | 1 | LSB | 12-bit mode, VDDS=1.71V-3.8V | 33 | |
| Active mode core current | Icore | 2.6 | mA | MCU running CoreMark from Flash at 48MHz, VDDS=3.0V, DCDC | 19 | ||
| Standby current | Icore | 0.71 | µA | RTC running, full RAM retention, LFOSC, DCDC | 19 | ||
| Shutdown current | Icore Shutdown | 165 | nA | No clocks running, no retention, IO wakeup enabled | 20 | ||
| Radio receive current | IRX | 5.3 | mA | 2440MHz, 1Mbps, GFSK, system bus off | 20 | ||
| Radio transmit current +8dBm | ITX | 10.7 | mA | +8dBm output power setting, 2440MHz, system bus off | 20 | ||
| BLE receiver sensitivity 1Mbps | -96.5 | dBm | BER = 10-3 | 22 |
CAD (KiCad official)
- Symbol:
CC2340R53E0RKPR - Footprint:
Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm - 3D model: VQFN-40(5x5) (KiCad packages3D, STEP)
- 3D model files:
cc2340r53e0rkpr-etched.step/cc2340r53e0rkpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cc2340r53e0rkpr.step/cc2340r53e0rkpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (78 pp, sha256
398fbbb11b90ace1, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).